LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 287 / 882

ML62Q1000 Series User's Manual
Chapter 7 Low Speed Time Base Counter
FEUL62Q1000 7-13
7.3 Description of Operation
7.3.1 Low-speed Time Base Counter Operation
The low-speed time base counter (LTBC) starts counting up from 0x0000 at the falling edge of the low-speed clock after
releasing the system reset, then generates T128HZ to T1HZ signals. Three factors can be chosen from among T128HZ to
T1HZ signals to generate periodical low-speed time base counter interrupt requests.
Values of T128HZ to T1HZ signals can be read from the LTBR register.
The low-speed time base counter interrupt request is generated at the falling edge of a signal chosen in the LTBINT
register.
When changing the assignment of interrupt signals in the LTBINT register, low-speed time base counter interrupt
requests (LTBCnINT) may be generated depending on timing to write to the register. Therefore, change the value in the
LTBINT register with the interrupt disabled in the IE67 register before changing the assignment of interrupt signals, and
clear the generated low-speed time base counter interrupt request bit (QLTBCn) to "0". (n = 0 to 2)
Figure 7-3 shows a sample program for changing the assignment of low-speed time base counter signals.
Figure 7-3 Sample Program for Changing Assignment of Low-speed Time Base Counter Signals
The time equivalent to one clock of the system clock is required for the low-speed time base counter interrupt request bit
(QLTBCn bit of IRQ67 register, n=0 to 2) to become "1" after changing the LTBINT register . Therefore, place one NOP
instruction after changing the LTBINT register.
When writing arbitrary data to the LTBR register, T128HZ to T1HZ signals of the LTBR register are all initialized to "0".
Depending on timing to write to the LTBR register, the signal assigned to the LTBINT register may change from "1" to
"0". Also a low-speed time base counter interrupt request may occur. Therefore, with the low-speed time base counter
interrupt disabled in the IE67 register, following writing to the LTBR register, clear the generated low-speed time base
counter interrupt request bit (the QLTBCn bit of the IRQ67 register) to "0". (n = 0 to 2)
Figure 7-4 shows a sample program for initializing the LTBR register.
Figure 7-4 Sample Program for Initializing LTBR Register
The time equivalent to one clock of the system clock is required for QLTBCn to become "1" after writing to the LTBR
register. Therefore, place one NOP instruction after writing to the LTBR register.
ELTBC0 = 0; // Disable LTBC0 interrupt
ELTBC1 = 0; // Disable LTBC1 interrupt
ELTBC2 = 0; // Disable LTBC2 interrupt
LTBINT = 0x0741; // Change assignment of interrupt signal
__asm("NOP"); // Waiting time
QLTBC0 = 0; // Clear QLTBC0
QLTBC1 = 0; // Clear QLTBC1
QLTBC2 = 0; // Clear QLTBC2
ELTBC0 = 1; // Enable LTBC0 interrupt
ELTBC1 = 1; // Enable LTBC1 interrupt
ELTBC2 = 1; // Enable LTBC2 interrupt
__DI(); // Disable interrupt (MIE=0)
LTBR = 0x00; // Reset LTBR
__asm("NOP"); // Waiting time
QLTBC0 = 0; // Clear QLTBC0
QLTBC1 = 0; // Clear QLTBC1
QLTBC2 = 0; // Clear QLTBC2
__EI(); // Enable interrupt (MIE=1)