LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 800 / 882

ML62Q1000 Series User's Manual
Chapter 29 Safety Function
FEUL62Q1000
29-5
29.2.3 SFR Guard Setting Register 0 (SFRGD0)
SFRGD0 is a special function register (SFR) used to disable writing the SFR by the CPU and the DMA Controller.
Data in the specified SFR area is protectable.
Address: 0xF0B4 (SFRGD0L/SFRGD0), 0xF0B5(SFRGD0H)
Access: R/W
Access size: 8/16bit
Initial value:
0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Word
SFRGD0
Byte
SFRGD0H SFRGD0L
Bit
- - - - - - - - - -
SGD05 SGD04 SGD03 SGD02 SGD01 SGD00
R/W R R R R R R R R R R R/W R/W R/W R/W R/W R/W
Initial
value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit No.
Bit symbol
name
Description
15 to 6 - Reserved bit
5 SGD05 This bit is used to disable WDTMOD register.
See Chapter 10 "Watch Dog Timer" for details of the register.
0: The SFR is writable and readable (Initial value)
1: The SFR is unwritable and readable
4 SGD04 This bit is used to disable BCKCONn register and BRECONn register (n=0 to 3).
See Chapter 4 "Power management" for details of the registers.
0: The SFR is writable and readable (Initial value)
1: The SFR is unwritable and readable
3 SGD03 This bit is used to disable RASFMOD register.
See Section 29.2.5 "RAM Parity Setting Register (RASFMOD) "for details of the register.
0: The SFR is writable and readable (Initial value)
1: The SFR is unwritable and readable
2 SGD02 This bit is used to disable SFRs described in Chapter 22 "Voltage Level Supervisor (VLS)".
0: The SFR is writable and readable (Initial value)
1: The SFR is unwritable and readable
1 SGD01 This bit is used to disable SFRs described in Chapter 6 "Clock Generation Circuit".
0: The SFR is writable and readable (Initial value)
1: The SFR is unwritable and readable
0 SGD00 This bit is used to disable SFRs described in Chapter 5 "Interrupt".
0: The SFR is writable and readable (Initial value)
1: The SFR is unwritable and readable