LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 605 / 882

ML62Q1000 Series User's Manual
Chapter 18 External Interrupt Function
FEUL62Q1000 18-11
18.2.6 Expanded External Interrupt Mode Register 1(EEIMOD1)
EEIMOD1 is a special function register (SFR) to choose dividing ratio of the sampling clock for the external interrupt
(EXI8 to EXI11).
Address
：
0xF0EA(EEIMOD1L/EEIMOD1), 0xF0EB(EEIMOD1H)
Access
：
R/W
Access size
：
8/16bit
Initial value
：
0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Word
EEIMOD1
Byte
EEIMOD1H EEIMOD1L
-Bit
- - - - - - - - -
EPG0D
IV2
EPG0D
IV1
EPG0D
IV0
- rsvd
- -
R/W R R R R R R R R R R/W R/W R/W R R/W R R
Initial
value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
No.
Bit symbol
name
Description
15 to 7 - Reserved bit
6 to 4 EPG0DIV2 to
EPG0DIV0 These bits are used to choose frequency dividing ratio for the sampling clock in the EXI8 to
EXI11.
000: No dividing (Initial value)
001: 1/2 of the sampling clock source
010: 1/4 of the sampling clock source
011: 1/8 of the sampling clock source
100: 1/16 of the sampling clock source
101: 1/32 of the sampling clock source
110: 1/64 of the sampling clock source
111: Do not use (No dividing)
3 - Reserved bit
2 rsvd Reserved bit. Write "0" to this bit.
1, 0 - Reserved bit
[Note]
Ÿ
In the STOP/STOP-D mode, no sampling is performed regardless of the values set in EPI3SM to EPI0SM
bits of EEIMOD0 register since the sampling clock stops. There is a time period
(*2)
in which interrupts
gets disabled.
(*2)
When entering STOP/STOP-D mode: Max.30us
When returning from STOP/STOP-D mode, the interrupt is disable until the sampling clock (LSCLK)
starts to be supplied. The start-up time for supplying clock is dependent of the clock or register settings.
For details about it, see Table 4-5
"
Wake-up Time from Standby Mode
"
in the Chapter 4
"
Power
Management " .