LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 688 / 882

ML62Q1000 Series User's Manual
Chapter 23 Successive Approximation Type A/D Converter
FEUL62Q1000
23-12
SA-ADC Mode Register (SADMOD) 23.2.6
SADMOD is a special function register (SFR) used to set the operation mode and operating clock frequency of the A/D
converter. The bit symbol "rsvd" means a reserved bit, write "0" to those bits.
Address: 0xF828(SADMODL/SADMOD), 0xF829(SADMODH)
Access: R/W
Access size: 8/16bit
Initial value:
0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Word
SADMOD
Byte
SADMODH SADMODL
Bit
rsvd rsvd rsvd rsvd rsvd rsvd rsvd SAINIT
SASHT
3
SASHT
2
SASHT
1
SASHT
0
SACK2 SACK1 SACK0 SALP
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit No. Bit symbol
name
Description
15 to 9 - reserved bit
8 SAINIT This bit is used to control whether or not to discharge the electrical charge remained in the
sample hold capacitor on the previous A/D conversion, before starting the next SA-ADC
conversion. When this bit is set to "1", the sample hold capacitance is discharged to Vss
level.
0: Start the A/D conversion without discharging the electrical charge accumulated in the
sample hold capacitor (Initial value)
1: Start the A/D conversion after discharging the electrical charge accumulated in the
sample hold capacitor
7 to 4 SASHT3 to
SASHT0
These bits are used to set the sampling time.
See Chapter 24.3.2 "A/D Conversion Time Setting" for details.
3 to 1 SACK2 to
SACK0
These bits are used to choose the frequency of the A/D conversion operating clock
(SAD_CLK). See Chapter 24.3.2 "A/D Conversion Time Setting" for the operating clock, A/D
conversion time and sample time.
000: 8MHz (Initial value)
001: 4MHz
010: 2MHz
011: 1MHz
100: 0.5MHz
101: Do not use
110: Do not use
111: 32kHz
0 SALP This bit is used to choose whether the A/D conversion is performed once only for each
channel or consecutively. The conversion interval time in the consecutive scan A/D
conversion mode is specified in the SADSTM register.
0: Single A/D conversion (Initial value)
1: Consecutive scan A/D conversion
[Note]
Ÿ
Write
"
0
"
to the SADMODH[7:1] bits. The operation when
"
1
"
is written to the bits is unguaranteed.