LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 707 / 882

ML62Q1000 Series User's Manual
Chapter 23 Successive Approximation Type A/D Converter
FEUL62Q1000
23-31
23.4 Notes on SA-ADC
Sampling Time Setting 23.4.1
The SA-ADC sampling time should satisfy the following formula:
Sampling time > 8 𝐶
𝑆𝑆𝑆𝑆𝑆𝑆
(
𝑅
1
+ 𝑅
2
)
R
1
: Input impedance of external resistor
R
2
: Internal resistor value which is the sum of the internal resistor and the ON register of the switch
C
SAMPLE
: Sample hold capacitor
The following diagram shows the equivalent circuit in this case:
VDD
R2[kΩ]
CSAMPLE[pF]
1.8 V
≤VDD≤2.2 V
500k 3.2pF
2.2 V
≤VDD≤2.7 V
100k 3.2pF
2.7 V
≤VDD≤4.5 V
8k 3.2pF
4.5 V
≤VDD≤5.5 V
7k 3.2pF
The values above are reference values.
If the sampling time above is unsatisfied, connect the external capacitor to satisfy the following formula:
External capacitor 𝐶
1
> 2
𝑛
𝐶
𝑆𝑆𝑆𝑆𝑆𝑆
Sampling time > 8 𝐶
𝑆𝑆𝑆𝑆𝑆𝑆
𝑅
2
n: Resolution of A/D converter
C
1
: External capacitor
The equivalent circuit when the external capacitor C
1
is connected is as follows:
Note that the voltage at the A/D input pin transitionally changes due to the external capacitor C
1
and the external resistor
R
1
. Therefore, when sampling data, wait until the voltage is stabilized. If the stabilization timing is unknown, perform
A/D conversion once, then wait for time constant τ (=R
1
C
1
) to 4τ or so and perform A/D conversion again. Confirm that
the difference between values is small, then sample data.
Internal equivalent circuit
C
SAMPLE
R
2
A/D
input pin
R
1
Signal source
Internal equivalent circuit
C
SAMPLE
R
2
A/D
input pin
R
1
Signal source C
1