LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 869 / 882

ML62Q1000 Series User’s Manual
Appendix E. List of Notes
FEUL62Q1000 E-10
[ ] When an error occurs in the start bit, the state returns to the reception waiting state.
[ ] Do not write the Un1FER bit, Un1OER bit, Un1PER bit and Un1FUL bit by using the bit symbol. Write
them by the byte-access.
See Section 11.3.1.6 "Timing in Clock Type 1 Slave Mode".
[ ] Even after the start interrupt has been generated, it is possible to write data to the transfer buffer
before the transfer is actually started (before the external clock is supplied). In that case, the data written
just before the start of the transfer is transferred.
[ ]To ensure that data is successfully transmitted, it is recommended that data is written when SnEN is "0"
or while the transfer of previous data is in progress (SnTXF=1).
See Section 11.3.2.3 "Direction of Transmit/Receive Data".
[ ] When the SUn_TXDn pin is set to the shared function in the reception mode, "H" level is output from
the SUn_TXDn pin.
See Section 11.3.2.10 "Receive Margin".
[ ] When designing the system, consider the difference of the baud rate between the transmission side
and reception side and delay of the start bit detection and adjust the baud rate in the UAn0BRT,
UAn1BRT, UAn0BRC, and UAn1BRC registers.
Chapter 12 I
2
C Bus Unit
See Section 12.1.4 "Pin Setting".
[ ] Use external pull-up resistors for SDA pin and SCL pin referring to the I
2
C bus specification. The
internal pull-up resistors unsatisfy the I2C bus specification. See the data sheet for each product for the
value of internal pull-up resistors.
[ ] If powering off this LSI in the slave mode, it disables communications of other devices on the I
2
C bus.
Remain the power to this LSI when it works as a slave mode until the master device is powered off.
[ ] When using the master function, do not connect multiple master devices on the I
2
C bus.
See Section 12.2.2 " I
2
C Bus Unit 0 Mode Register (I2U0MSS)".
[ ] Do not write to SFRs for slave function in the master mode and do not write SFRs for master function
in the slave mode.
[ ] When using the master function, do not connect multiple master devices on the I
2
C bus.
[ ] If powering off this LSI in the slave mode, it disables communications of other devices on the I
2
C bus.
Remain the power to this LSI when it works as a slave mode until the master device is powered off.
[ ] When using the salve function, switch the system clock to the high-speed clock if releasing the
communication wait status.
[ ] When using the salve function with multi-slaves connected to the I
2
C bus, conform to the following
conditions while enabling the I
2
C bus function (I2U0MD=1 and I2US0EN=1) regardless communicating
or not.
- Specify SYS_CLK as four time or higher than the I
2
C bus communication speed.
SYS_CLK needs to be 500kHz or higher when the I
2
C bus communication speed is 100kbps.
SYS_CLK needs to be 2MHz or higher when the I
2
C bus communication speed is 400kbps.
SYS_CLK needs to be 4MHz or higher when the I
2
C bus communication speed is 1Mbps.
- Do not use LSCLK as the SYS_CLK.
- Do not enter HALT-H mode while enabling the I
2
C bus function.
See Section 12.2.6 "I
2
C Bus 0 Control Register (Master) (I2UM0CON)".
[ ] Do not update the I2UM0ACT bit by using the bit symbol. Update it by using a byte access, not so that
unintented bits are changed by the bit access instructions.
[ ] When the I2UM0ST bit is "1", write the I2UM0CON register in the control register setting wait state.