LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 452 / 882

ML62Q1000 Series User's Manual
Chapter 11 Serial Communication Unit
FEUL62Q1000 11-50
11.3.2.5 Receive Operation
The following shows the reception procedure in the UART full-duplex communication mode. Figure 11-16 shows the
operation timing for reception.
Ÿ
To prepare the communication (settings common to transmission/reception for full-duplex communication):
−
Choose the full-duplex communication mode in the serial communication unit n mode register (SUnMOD).
−
If using the transmission interval function, set the serial communication unit n transmission interval setting
register (SUnDLYL).
−
Choose the communication mode with the UARTn0 mode register (UAn0MOD).
−
Set the baud rate with the UARTn0 baud rate register (UAn0BRT) and the UARTn0 baud rate adjustment
register (UAn0BRC).
−
Set the shared function for the general-purpose port to use for UART communication, then choose the pin
mode.
−
Clear the request bit for the serial communication unit n0 and n1 interrupts. (QSIUn0=0, QSIUn1=0)
−
Enable the serial communication unit n0 and n1 interrupts. (ESIUn0=1, ESIUn1=1)
−
Read the serial communication unit n transmission/reception buffer L (SDnBUFL) to prevent a false detection
of overrun errors. The read data can be discarded.
−
Write "0xFF" to the UARTn0 status register (UAn0STAT) to clear each flags.
Ÿ
To start reception:
−
Enable transmission/reception by setting Un0EN bit of the serial communication unit n control register
(SUnCONL) to "1". (1)
−
Start detecting the start bit input to the SUn_RXD0 pin.
−
When "L" level of the SUn_RXD pin is detected (2), the baud rate generator starts generating the transfer
clock. When "H" level is received in the middle of the start bit, it is recognized as an unintended operation and
the detection of the start bit is resumed.
−
When "L" level is received in the middle of the start bit, the reception operation is started. Data input to
SUn_RXD0 at the rising edge of the internal transfer clock is loaded to the shift register.
−
Once loading received data and parity bits is completed, the loaded data is transferred to the serial
communication unit n transmission/reception buffer (SDnBUFL). (3)
−
In the middle of the stop bit (4), the serial communication unit n0 interrupt (SIUn0INT) is generated, and a
framing error (stop bit error) and parity bit error are determined. If an error is detected, applicable bits
(Un0FER and Un0PER) of the UARTn0 status register (UAn0STAT) are set to "1". Also, the operation
simultaneously shifts to the detection of the subsequent start bit.
−
When continuously receiving data, if SDnBUFL is overwritten with the subsequently received data before the
CPU reads the received data (SDnBUFL register), the overrun error (Un0OER) bit of the UAnSTAT register
becomes "1".
Ÿ
Reception end
−
If terminating the UART reception, set the Un0EN bit of the SUnCONL register to "0". If resetting the Un0EN
bit to "0" in the middle of the reception, the received data may be destroyed.
Figure 11-16 Operation Timing in Reception
Un0E
SUn_RXD
Internal
transfer
Clock
SIUn0INT
Un0PER
Un0FER
Un0OER
BRT
Start 0
1 2 7
Parity
Start
BRT
Stop 0 1 6 7 Parity
Stop
2nd data
1st data
Start bit detected
↑
(2)
↑
(1)
↑
(3)
↑
(4)
Error detection
interrupt request
↑
(5)
↓If an error detected
Start 0 2 7 Parity
1
Start
Stop
0
1 6 7 Parity
Stop
Transmission/
reception buffer
Shift register
(input stage)
↑
(4)