LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 272 / 882

ML62Q1000 Series User's Manual
Chapter 6 Clock Generation Circuit
FEUL62Q1000 6-24
Figure 6-14 shows the flow chart of the system clock switching (HSCLK
à
LSCLK).
Figure 6-14 Flow Chart of System Clock Switching (HSCLK
à
LSCLK)
[Note]
Ÿ
While the CPU is running with the low-speed clock, if running the peripheral circuits with the high-speed
clock which can frequently generate interrupts, the operation may fail to function properly due to the
CPU becoming incapable of processing interrupts in time. If interrupts frequently occur for reasons
such as short interrupt cycles of peripheral circuits, take into account the operating frequency of the
CPU so that it can process interrupts in time.
FCON=0x00 : When stopping the high-speed oscillation and switching
the system clock to the low-speed clock
FCON=0x02 : When maintaining operation of the high-speed oscillation
and switching the system clock to the low-speed clock
The system clock switches to the low-speed clock.
The state of both the low-speed clock
and the high-speed clock are oscillating
Setting of FCON
Low-speed operation mode