LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 349 / 882

ML62Q1000 Series User's Manual
Chapter 9 Functional Timer (FTM)
FEUL62Q1000 9-29
9.2.13 FTMn Interrupt Status Register (FTnINTS: n = 0 to 7)
FTnINTS is a specific function register (SFR) to indicate the interrupt status of FTMn.
The bit5 to bit0 is reset to "0" by writing "1" to the same number of bit in the MCINTCL register.
The FTnINTS is a read-only register.
Address: 0xF4B0(FT0INTSL/FT0INTS), 0xF4B1(FT0INTSH),
0xF4B2(FT1INTSL/FT1INTS), 0xF4B3(FT1INTSH),
0xF4B4(FT2INTSL/FT2INTS), 0xF4B5(FT2INTSH),
0xF4B6(FT3INTSL/FT3INTS), 0xF4B7(FT3INTSH),
0xF4B8(FT4INTSL/FT4INTS), 0xF4B9(FT4INTSH),
0xF4BA(FT5INTSL/FT5INTS), 0xF4BB(FT5INTSH),
0xF4BC(FT6INTSL/FT6INTS), 0xF4BD(FT6INTSH),
0xF4BE(FT7INTSL/FT7INTS), 0xF4BF(FT7INTSH)
Access: R
Access size: 8/16 bit
Initial value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Word
FTnINTS
Byte
FTnINTSH FTnINTSL
Bit
− − − − − − − − − −
FTnIS
ES
FTnIS
TR
FTnIS
TS
FTnIS
B
FTnIS
A
FTnIS
P
R/W R R R R R R R R R R R R R R R R
Initial
value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit no.
Bit symbol
name
Description
15 to 6 - Reserved bit
5 FTnISES This bit is used to indicate the state of the emergency stop interrupt of FTMn.
0: Emergency stop interrupt has not occurred (initial value)
1: Emergency stop interrupt has occurred
This bit is cleared when writing 1 to FTnICES bit of FTnINTC register.
4 FTnISTR This bit is used to indicate the state of the trigger counter start interrupt of FTMn.
0: Trigger counter start interrupt has not occurred (initial value)
1: Trigger counter start interrupt has occurred
This bit is cleared when writing 1 to FTnICTR bit of FTnINTC register.
3 FTnISTS This is a bit to indicate the state of the trigger counter stop interrupt of FTMn.
0: Trigger counter stop interrupt has not occurred (initial value)
1: Trigger counter stop interrupt has occurred
This bit is cleared when writing 1 to FTnICTS bit of FTnINTC register.
2 FTnISB This is a bit to indicate the state of the event timing B interrupt of FTMn.
In CAPTURE mode, it indicates the status of storing the capture data into the FTnEB register.
Ÿ
TIMER, PWM1, PWM2 mode
0: Event timing B interrupt has not occurred (initial value)
1: Event timing B interrupt has occurred
This bit is cleared by writing "1" to the FTnIB register.
Ÿ
CAPTURE mode
0: Capture B interrupt has not occurred
1: Capture B interrupt has occurred
Indicates that the captured data is stored to the FTnEB register.
This bit is cleared by writing "1" to FTnICB bit of FTnINTC register or by reading the
FTnEB register.