LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 705 / 882

ML62Q1000 Series User's Manual
Chapter 23 Successive Approximation Type A/D Converter
FEUL62Q1000
23-29
Table 23-4 A/D conversion time when using the internal reference voltage as reference voltage
SADMOD
Conversion
clock count
Conversion time
SAD_CLK
SASHT[3:0] 32kHz 0.5MHz 1MHz 2MHz 4MHz 8MHz
0 0 0 0 14
427 μs
Prohibited
Prohibited
Prohibited
Prohibited
Prohibited
0 0 0 1 15
Prohibited
0 0 1 0 16
0 0 1 1 17
0 1 0 0 18
0 1 0 1 19
0 1 1 0 20
0 1 1 1 21
1 0 0 0 29
58 μs
1 0 0 1 45
90 μs 45 μs
1 0 1 0 61
122 μs 61 μs
1 0 1 1 77
154 μs 77 μs 38.5 μs
1 1 0 0 93
186 μs 93 μs 46.5 μs
1 1 0 1 109
218 μs 109 μs 54.5 μs
1 1 1 0 125
250 μs 125 μs 62.5 μs
1 1 1 1 141
282 μs 141 μs 70.5 μs 35.25 μs
[Note]
Ÿ
If choosing to start A/D conversion after discharging the internal sample hold capacitive electrical
charge to the VSS level at the start of A/D conversion, the A/D conversion time shown in Table 23-3 and
23-4 is increased by two clocks of the conversion clock (SAD_CLK).
Ÿ
The A/D conversion time does not include the clock frequency error.
Table 23-5 Sampling time when using V
DD
or V
REF
pin as reference voltage
SADMOD
Sample/
hold
clock count
Sampling time
SAD_CLK
SASHT[3:0] 32kHz 0.5MHz 1MHz 2MHz 4MHz 8MHz
0 0 0 0 1
30 μs 2 μs
Prohibited
Prohibited
Prohibited
Prohibited
0 0 0 1 2
Prohibited
4 μs 2 μs
0 0 1 0 3
6 μs 3 μs 1.5 μs
0 0 1 1 4
8 μs 4 μs 2 μs 1 μs
0 1 0 0 5
10 μs 5 μs 2.5 μs 1.25 μs 0.625 μs
0 1 0 1 6
12 μs 6 μs 3 μs 1.5 μs 0.75 μs
0 1 1 0 7
14 μs 7 μs
3.5
μs 1.75 μs 0.875 μs
0 1 1 1 8
16 μs 8 μs 4 μs 2 μs 1 μs
1 0 0 0 16
32 μs 16 μs 8 μs 4 μs 2 μs
1 0 0 1 32
64 μs 32 μs 16 μs 8 μs 4 μs
1 0 1 0 48
96 μs 48 μs 24 μs 12 μs 6 μs
1 0 1 1 64
128 μs 64 μs 32 μs 16 μs 8 μs
1 1 0 0 80
160 μs 80 μs 40 μs 20 μs 10 μs
1 1 0 1 96
192 μs 96 μs 48 μs 24 μs 12 μs
1 1 1 0 112
224 μs 112 μs 56 μs 28 μs 14 μs
1 1 1 1 128
256 μs 128 μs 64 μs 32 μs 16 μs