LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 21 / 882

ML62Q1000 Group User's Manual
Chapter 1 Overview
FEUL62Q1000 1-4
l
Reset
−
RESET_N pin reset
−
Reset by power-on detection
−
Reset by the 2
nd
watchdog timer (WDT) overflow
−
Reset by WDT counter clear during the clear invalid period
−
Reset by RAM parity error
−
Reset by unused ROM access
−
Reset by voltage level detection 0 (VLS0)
−
The software reset by BRK instruction (reset CPU only)
−
Reset to the peripherals by the block reset control registers
l
Power management
−
HALT mode: CPU stops executing instruction, clock oscillations and peripheral circuits remain previous states
−
HALT-H mode: CPU stops executing instruction, high-speed clock oscillation stops and peripheral circuits
working with low-speed clock remain previous states
−
STOP mode: CPU stops executing instruction, both high-speed oscillation and low-speed oscillation stop.
−
STOP-D mode: CPU stops executing instruction, both high-speed oscillation and low-speed oscillation stop.
(V
DDL
) goes down to reduce the current consumption (RAM data is retained).
−
Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, 1/8, 1/16 or
1/32 of the oscillation clock)
−
Block Control Function: Powers down the circuits of unused function blocks (reset the block or stop supplying
the clock)
l
Interrupt controller
−
External interrupt : Max. 12
−
Non-maskable interrupt source: 1 (Internal sources: WDT)
−
Maskable interrupt sources: max.52 (Internal sources: max.40, External sources: 12)
−
Four step interrupt levels
l
Watchdog timer(WDT)
−
Operating clock is selectable (1kHz WDT independent clock or divided clock of internal 32.768kHz RC
oscillation)
−
Overflow period: 8 types selectable (7.8ms, 15.6ms, 31.3ms, 62.5ms, 125ms, 500ms, 2000ms and
8000ms@32.768kHz)
−
Enabling or disabling the window function is selectable (The clear enable period is 50% or 75% of overflow
period)
−
WDT operation is selectable by code option (Enable or Disable)
−
Readable WDT counter (WDT counter monitor function)
−
The first overflow generates the WDT interrupt, and the second overflow generates the WDT reset when the
counter clear enable period is 100% of overflow period
−
The first overflow generates the WDT reset when the counter clear enable period is 50% or 75% of overflow
period
−
The invalid clear reset generated when the WDT counter is cleared out of the WDT counter clear enable period.
l
DMA(Direct Memory Access) controller
−
Channel : 2ch
−
Transfer unit: 8bit/16bit
−
Transfer count: 1 to 1024
−
Transfer type: 2 cycle transfer
−
Transfer mode: Single transfer mode (Fixed address, address increments and address decrements)
−
Transfer target: SFR
ßà
RAM (Transfer from/to Flash is not supported)
−
Transfer request trigger: Serial communication unit, Successive approximation type A/D converter, 16bit timer,
Functional timer and External pin.
l
Low-speed Time base counter
−
Devide the Low-speed clock(LSCLK) and generate 128Hz to1Hz internal pulse signals
−
Three interrupts are selectable out of eight frequency periodical interrupts (128Hz, 64Hz, 32Hz, 16Hz, 8Hz, 4Hz,
2Hz and 1Hz)
−
The time base clock output (1Hz or 2Hz) from general purpose ports (TBCOUT1).
−
Frequency adjust function (Adjust range: approx. -488ppm to +488ppm, adjust resolution: approx. 0.119ppm)
(ML62Q1500 and ML62Q1700 group)