LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 704 / 882

ML62Q1000 Series User's Manual
Chapter 23 Successive Approximation Type A/D Converter
FEUL62Q1000
23-28
A/D Conversion Time Setting 23.3.3
For the A/D conversion time and sampling time, the conversion time and configurable range vary depending on the
following settings:
Ÿ
Reference voltage set using the reference voltage control register (VREFCON)
Ÿ
A/D conversion operation clock (SAD_CLK) set using the SA-ADC mode register (SADMOD)
Table 23-3 and 23-4 show SADMOD register setting vs the A/D conversion time. Table 23-5 and 23-6 show SADMOD
register setting (SASHT3 to SASHT0 bits, SACK2 to SACK0 bits) vs the sampling time.
See the following description for each table vs the reference voltage.
Table 23-3 A/D Conversion time when using V
DD
or V
REF
pin as reference voltage
SADMOD
Conversion
clock count
Conversion time
SAD_CLK
SASHT[3:0] 32kHz 0.5MHz 1MHz 2MHz 4MHz 8MHz
0 0 0 0 14
427 μs 28 μs
Prohibited
Prohibited
Prohibited
Prohibited
0 0 0 1 15
Prohibited
30 μs 15 μs
0 0 1 0 16
32 μs 16 μs 8 μs
0 0 1 1 17
34 μs 17 μs 8.5 μs 4.25 μs
0 1 0 0 18
36 μs 18 μs 9 μs 4.5 μs 2.25 μs
0 1 0 1 19
38 μs 19 μs 9.5 μs 4.75 μs 2.375 μs
0 1 1 0 20
40 μs 20 μs 10 μs 5 μs 2.5 μs
0 1 1 1 21
42 μs 21 μs 10.5 μs 5.25 μs 2.625 μs
1 0 0 0 29
58 μs 29 μs 14.5 μs 7.25 μs 3.625 μs
1 0 0 1 45
90 μs 45 μs 22.5 μs 11.25 μs 5.625 μs
1 0 1 0 61
122 μs 61 μs 30.5 μs 15.25 μs 7.625 μs
1 0 1 1 77
154 μs 77 μs 38.5 μs 19.25 μs 9.625 μs
1 1 0 0 93
186 μs 93 μs 46.5 μs 23.25 μs
11.625
μs
1 1 0 1 109
218 μs 109 μs 54.5 μs 27.25 μs 13.625 μs
1 1 1 0 125
250 μs 125 μs 62.5 μs 31.25 μs 15.625 μs
1 1 1 1 141
282 μs 141 μs 70.5 μs 35.25 μs 17.625 μs