LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 359 / 882

ML62Q1000 Series User's Manual
Chapter 9 Functional Timer (FTM)
FEUL62Q1000 9-39
9.3.2 Counter Operation (Common to All Modes)
The operation of FTM's internal counter is common to each mode.
It counts up to the setting value of the FTnP register.
In the repeat mode (the FTnOST bit of the FTnMOD register is "0"), the counter is cleared at the time of overflow, then
continues the counting operation again.
In the one-shot mode (the FTnOST bit of the FTnMOD register is "1"), the counter is cleared at the time of overflow,
then stops the counting operation.
Starting/stopping the counting operation can be executed through the software or a trigger event.
9.3.2.1 Starting/Stopping Counting via Software
When writing "1" to the FTnSTR bit of the FTCSTR register, the FTnSTA bit of the FTnSTAT register showing the
count status becomes "1", and the counting operation is started.
In the one-shot mode (the FTnOST bit of the FTnMOD register is "1"), the counting operation is stopped by overflow.
The FTnSTA bit of the FTnSTAT register showing the count status automatically becomes "0".
When writing "1" to the FTnSTP bit of the FTCSTP register while the counter operation is in progress (the FTnSTA bit
of the FTnSTAT register showing the count status is "1"), the counter stops its operation. To confirm the stop of the
counter, check by the software that the FTnSTA bit of the FTnSTAT register is reset to "0". The counter value is
maintained while the counter is not working.
After the counter is stopped, if "1" is written to the FTnSTR bit of the FTCSTR register again, it continues counting from
the value at the time it stopped.
To clear the counter, execute writing to the FTnC register while it is stopped.
If subsequently restarting the counter, confirm that the FTnC register is reset to "0x0000", then write "1" to the FTnSTR
bit of the FTCSTR register.
9.3.2.2 Starting/Stopping Counting by Trigger Event
Writing "1" to the FTnETG bit of the FTCSTR register enables the counter operation to be controlled by triggers.
Trigger choice, etc. can be executed through the configuration of FTnTRG0 and FTnTRG1 registers.
The source of a trigger event can be chosen from EXTRG0 to EXTRG7, CMP0D, TMH0TRG to TMH5TRG, or
FTMnTRG.
Depending on the chosen trigger event, an operation (counter start, counter stop, counter start/stop and counter clearing)
can be chosen.