LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 759 / 882

ML62Q1000
Series User's Manual
Chapter 27 LCD Driver
FEUL62Q1000 27-9
27.2.2 Bias Control Register(BIASCON)
BIASCON is a special function register (SFR) to adjust the display contrast in 32 levels in the internal boosting mode.
BIASCONL is a special function register (SFR) used to control the bias generation circuit.
Write the BIASCONL when the display turns off (when the LMD1 bit and LMD0 bit of DPSCON register are "0").
Writing to the BIASCONL is disabled in other modes.
Address: 0xF0F0(BIASCONL/BIASCON)
，
0xF0F1(BIASCONH)
Access: R/W
Access size: 8/16bits
Initial value: 0x0008
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Word
BIASCON
Byte
BIASCONH BIASCONL
But
− − −
LCN4 LCN3 LCN2 LCN1 LCN0
BTSE
L1
BTSE
L0
DSM
D1
DSM
D0
BSN2 BSN1 BSN0
BSO
N
R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
value
0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Bit
No.
Bit name Description
15 to
13 Reserved bits -
12 to 8 LCN4 to LCN0 These bits are used to adjust the display contrast in 32 voltage levels.
It is adjustable by controlling the VL1 voltage.
See the electrical characteristics in the data sheet for more details about the voltage level.
Contrast (voltage)
0x1F: Thick (high)
0x1E:
：
to
0x01:
：
0x00: Thin (low) (initial value)
7, 6 BTSEL1,
BTSEL0 These bits are used to select the means of bias generation circuit operation.
Select the external supply type when driving the LED.
00: External supply type (initial value)
01: Internal boosting type
10: External supply capacitive dividing type
11: Internal capacitive dividing type
5 DSMD1 This bit is used to select the display device.
0: LCD (initial value)
1: LED
4 DSMD0 This bit is used to select the white & black reverse display mode.
0: Normal display (initial value)
1: Normal display (initial value)
3 to 1 BSN2 to BSN0 These bits are used to select the clock for boosting the voltage in the bias generation circuit.
000: LSCLK(32.768kHz)
001: 1/2 LSCLK(16.384kHz)
010: 1/4 LSCLK(8.192kHz)
011: 1/8 LSCLK(4.096kHz)
100: 1/16 LSCLK(2.048kHz) (Initial)
101: 1/32 LSCLK(1.02kHz)
110: 1/64 LSCLK(512Hz)