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ML62Q1000 Series User's Manual 

Chapter 5 Interrupts 

FEUL62Q1000 

5-40 

5.3.1 Maskable Interrupt Processing 

When an interrupt is generated with MIE set to "1", the following process is executed by hardware and the CPU goes to 
the interrupt routine. 
 
1.

 

Save the program counter (PC) in ELR1. 

2.

 

Save CSR in ECSR1 (not processed if the program memory size is 64 Kbytes or less). 

3.

 

Save PSW in EPSW1. 

4.

 

Set ELEVEL of PSW to "1". 

5.

 

Reset the MIE flag to "0". 

6.

 

Set CSR to "0" (not processed if the program memory size is 64 Kbytes or less). 

7.

 

Transfer the value of the interrupt vector address to the program counter (PC). 

 

5.3.2 Non-Maskable Interrupt Processing 

When an interrupt occurs, the following process is executed by hardware and the CPU goes to the interrupt routine   
regardless of the value of MIE. 
 
1.

 

Save the program counter (PC) in ELR2. 

2.

 

Save CSR in ECSR2 (not processed if the program memory size is 64 Kbytes or less). 

3.

 

Save PSW fin EPSW2. 

4.

 

Set ELEVEL of PSW to "2". 

5.

 

Set CSR to "0" (not processed if the program memory size is 64 Kbytes or less). 

6.

 

Transfer the value of the interrupt vector address to the program counter (PC). 

 

5.3.3 Software Interrupt Processing 

The software interrupt is arbitrarily produced in software. 
When the SWI instruction is performed within the program, a software interrupt occurs, the following process is 
performed by hardware, and the CPU goes to the software interrupt routine. The vector table is specified with the SWI 
instruction. 
 
1.

 

Save the program counter (PC) in ELR1. 

2.

 

Save CSR in ECSR1 (not processed if the program memory size is 64 Kbytes or less). 

3.

 

Save PSW in EPSW1. 

4.

 

Set ELEVEL of PSW to "1". 

5.

 

Set the MIE flag to "0". 

6.

 

Set CSR to "0" (not processed if the program memory size is 64 Kbytes or less). 

7.

 

Transfer the value of the interrupt vector address to the program counter (PC). 

 
See "nX-U16/100 Core Instruction Manual" for MIE, the program counter (PC), ELR1, CSR, ECSR1, PSW, EPSW1, 
ELEVEL, ELR2, ECSR2, EPSW2 and vector table. 

 

Summary of Contents for ML62Q1000 Series

Page 1: ...ML62Q1000 Series ML62Q1300 Group ML62Q1500 Group ML62Q1700 Group User s Manual Issue Date Dec 11 2018 FEUL62Q1000 01...

Page 2: ...designed to be radiation tolerant 7 For use of our Products in applications requiring a high degree of reliability as exemplified below please contact and consult with a LAPIS Semiconductor represent...

Page 3: ...the unused pins are described in the chapters follow the instruction 2 STATE AT POWER ON At the power on the data in the internal registers and output of the ports are undefined until the power supply...

Page 4: ...erter and also on the specifications of the assembler language n CCU8 User s Manual Description on the method of operating the compiler n CCU8 Programming Guide Description on the method of programmin...

Page 5: ...that Read Write attribute R indicates that data can be read and W indicates that data can be written R W indicates that data can be read or written MSB The highest bit of 16 bit register LSB The lowes...

Page 6: ...3 3 How to Use Multiplier Divider 2 11 2 4 Memory Space 2 12 2 5 Program Memory Space 2 13 2 6 Data Memory Space 2 16 2 7 Description of Registers 2 36 2 7 1 List of Registers 2 36 2 7 2 Data Segment...

Page 7: ...Standby Mode 4 26 4 3 8 Block Control Function 4 28 Chapter 5 5 Interrupts 5 1 5 1 General Description 5 1 5 1 1 Features 5 1 5 2 Description of Registers 5 2 5 2 1 List of Registers 5 2 5 2 2 Interr...

Page 8: ...n 6 15 6 3 1 Low Speed Clock 6 15 6 3 2 High Speed Clock 6 21 6 3 3 WDT Clock 6 22 6 3 4 Switching of System Clock 6 23 6 3 5 Switching Low speed Clock 6 25 Chapter 7 7 Low Speed Time Base Counter 7 1...

Page 9: ...TMn Clock Register FTnCLK n 0 to 7 9 20 9 2 10 FTMn Trigger Register 0 FTnTRG0 n 0 to 7 9 22 9 2 11 FTMn Trigger Register 1 FTnTRG1 n 0 to 7 9 25 9 2 12 FTMn Interrupt Enable Register FTnINTE n 0 to 7...

Page 10: ...MOD 11 28 11 2 10 UARTn0 Baud Rate Register UAn0BRT 11 30 11 2 11 UARTn1 Baud Rate Register UAn1BRT 11 30 11 2 12 UARTn0 Baud Rate Adjustment Register UAn0BRC 11 31 11 2 13 UARTn1 Baud Rate Adjustment...

Page 11: ...ter Operation 13 13 13 3 2 Communication Operation Timing 13 17 13 3 3 Operation Waveforms 13 19 Chapter 14 14 DMA Controller 14 1 14 1 General Description 14 1 14 1 1 Features 14 1 14 1 2 Configurati...

Page 12: ...17 1 2 Configuration 17 3 17 1 3 List of Pins 17 5 17 2 Description of Registers 17 8 17 2 1 List of Registers 17 8 17 2 2 Port n Data Register PnD n 0 to 9 A B 17 15 17 2 3 Port n Mode Register 01 P...

Page 13: ...alculation End Address Setting Register CRCEAD 19 5 19 2 4 Automatic CRC Calculation Start Segment Setting Register CRCSSEG 19 6 19 2 5 Automatic CRC Calculation End Segment Setting Register CRCESEG 1...

Page 14: ...lt Register SADR 23 9 23 2 4 SA ADC Upper Lower Limit Status Register 0 SADULS0 23 10 23 2 5 SA ADC Upper Lower Limit Status Register 1 SADULS1 23 11 23 2 6 SA ADC Mode Register SADMOD 23 12 23 2 7 SA...

Page 15: ...on method 25 21 25 4 3 Communication command 25 22 25 4 4 Transition Command to ISP Mode 25 23 25 4 5 Flash Memory Handling 25 24 Chapter 26 26 Code Option 26 1 26 1 General Description 26 1 26 1 1 Fu...

Page 16: ...Register RAMGD 29 4 29 2 3 SFR Guard Setting Register 0 SFRGD0 29 5 29 2 4 SFR Guard Setting Register 1 SFRGD1 29 6 29 2 5 RAM Parity Setting Register RASFMOD 29 8 29 2 6 Communication Test Setting R...

Page 17: ...Chapter 1 Overview...

Page 18: ...lash programming in production line The product lists are shown below 1 The products use SuperFlash technology licensed from Silicon Storage Technology Inc SuperFlash is a registered trademark of Sili...

Page 19: ...00 TQFP100 256Kbyte 16Kbyte 4Kbyte ML62Q1727 ML62Q1737 ML62Q1747 192Kbyte ML62Q1726 ML62Q1736 ML62Q1746 160Kbyte ML62Q1725 ML62Q1735 ML62Q1745 128Kbyte 16Kbyte ML62Q1734 ML62Q1744 8Kbyte ML62Q1704 ML6...

Page 20: ...lash memory area Rewrite count 100 cycles Rewrite unit 32bit 4byte Erase unit 16Kbyte 1Kbyte Erase Rewrite temperature 0 C to 40 C Data Flash memory area Rewrite count 10 000 cycles Rewrite unit 8bit...

Page 21: ...perating clock is selectable 1kHz WDT independent clock or divided clock of internal 32 768kHz RC oscillation Overflow period 8 types selectable 7 8ms 15 6ms 31 3ms 62 5ms 125ms 500ms 2000ms and 8000m...

Page 22: ...el l 16bit General timers Channel Max 8ch 8 bits timer mode and 16 bit timer mode 1ch 16 bit timer is configurable as 2ch 8 bit timer Same start stop is avaible with different channels This function i...

Page 23: ...ared functions Input port Max 2 Including a shared function External interrput function 12 LED driver port Max 91 Carrier frequency output function used for IR communication l Successive approximation...

Page 24: ...g 3com seg Max ML62Q1733 ML62Q1734 ML62Q1735 ML62Q1736 ML62Q1737 45seg 8com com Max 50seg 3com seg Max ML62Q1743 ML62Q1744 ML62Q1745 ML62Q1746 ML62Q1747 60seg 8com com Max 65seg 3com seg Max 1 Five pi...

Page 25: ...55 1556 1557 xxxGA Blank part ML62Q1550 1551 1552 1553 1554 1555 1556 1557 NNNGA 80 pin plastic QFP ML62Q1563 1564 1565 1566 1567 xxxGA Blank part ML62Q1563 1564 1565 1566 1567 NNNGA 100 pin plastic T...

Page 26: ...2 Q 13 6 7 xxx TB Package Type GD WQFN MB SSOP TB TQFP TD TSSOP ROM Code Number NNN Blank xxx Custom Code Number Program Memory Size 3 16Kbyte 4 24Kbyte 5 32Kbyte 6 48Kbyte 7 64Kbyte Pin Count 2 16pin...

Page 27: ...kage Type GA QFP TB TQFP ROM Code Number NNN Blank xxx Custom Code Number Program Memory Size 0 32K byte 1 48K byte 2 64K byte 3 96K byte 4 128K byte 5 160K byte 6 192K byte 7 256K byte Pin Count 3 48...

Page 28: ...kage Type GA QFP TB TQFP ROM Code Number NNN Blank xxx Custom Code Number Program Memory Size 0 32K byte 1 48K byte 2 64K byte 3 96K byte 4 128K byte 5 160K byte 6 192K byte 7 256K byte Pin Count 3 48...

Page 29: ...s unit Master Slave channel I 2 C bus interface Master only channel 10bit Successive type A D converter channel Analog comparator channel Analog comparator input pin 8bit D A converter channel ML62Q13...

Page 30: ...e type A D converter channel Analog comparator channel Analog comparator input pin 8bit D A converter channel ML62Q1530 48 3 1 2 42 41 32 10 6 6 1 2 1 2 12 2 4 1 ML62Q1531 ML62Q1532 ML62Q1533 ML62Q153...

Page 31: ...s unit Master Slave channel I 2 C bus interface Master only channel 10bit Sussesive type A D converter channel Analog comparator channel Analog comparator input pin 8bit D A converter channel ML62Q170...

Page 32: ...er 1 Overview FEUL62Q1000 1 15 3 Shared with pins for crystal oscillation 4 The LCD common segment shared pins are shared for common or segment selectable by setting a SFR 5 All LCD drive pins are sha...

Page 33: ...ntroller On Chip ICE VDD VSS ALU Program memory Flash INT Serial Unit RAM Power Circuit VDDL TEST RESET_N TEST0 2 Clock Generation Circuit OUTLSCLK OUTHSCLK BZ0P BZ0N I 2 C Bus Unit TMH0 5OUT I2CU0_SD...

Page 34: ...SU0 5_RXD1 1 SU0 5_TXD1 1 16bit Function al Timer INT EXTRIG0 7 FTM0 7P FTM0 7N INT Time base Counter INT Data Flash INT FLASH Controller Interrupt Low speed RC Oscillation WDT INT High speed PLL Osci...

Page 35: ...er INT TEST RESET_N TEST0 2 Data Flash Clock Generation Circuit INT OUTLSCLK OUTHSCLK FLASH Controller Low speed RC Oscillation Interrupt High speed PLL Oscillation WDT INT INT VLS INT Low speed Cryst...

Page 36: ...23 1324 1325 16pin SSOP Figure 1 7 Pin Layout of ML62Q1323 1324 1325 16pin SSOP VDD VSS VDDL RESET_N P00 TEST0 P02 EXI0 EXTRG0 P04 EXI2 EXTRG2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 P27 EXI7 EXTRG7 P2...

Page 37: ...16pin WQFN Figure 1 8 Pin Layout of ML62Q1323 1324 1325 16pin WQFN 13 14 15 16 8 7 6 5 TOP VIEW WQFN16 P13 P04 EXI2 EXTRG2 P03 EXI1 EXTRG1 P02 EXI0 EXTRG0 P23 EXI5 EXTRG5 P26 EXI6 EXTRG6 P27 EXI7 EXTR...

Page 38: ...ure 1 9 Pin Layout of ML62Q1333 1334 1335 20pin TSSOP TOP VIEW TSSOP20 RESET_N P00 TEST0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDDL VSS VDD P33 P02 EXI0 EXTRG0 P04 EXI2 EXTRG2 P13 P17 EXI...

Page 39: ...ut of 1345 1346 1347 24pin WQFN 19 20 21 22 23 24 1 2 3 4 5 6 12 11 10 9 8 7 18 17 16 15 14 13 TOP VIEW WQFN24 P13 P12 P05 P04 EXI2 EXTRG2 P03 EXI1 EXTRG1 P02 EXI0 EXTRG0 P24 P25 P26 EXI6 EXTRG6 P27 E...

Page 40: ...n TQFP TOP VIEW TQFP32 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 P13 P12 P11 P10 P07 P06 P05 P04 EXI2 EXTRG2 24 23 22 21 20 19 18 17 P16 P15 P14 V DD V SS V DDL RESET_N P00 TEST0...

Page 41: ...in WQFN 27 28 29 30 31 32 1 2 3 4 5 6 14 13 12 8 7 24 23 22 21 20 19 TOP VIEW WQFN32 P11 P10 P07 P06 P05 P04 EXI2 EXTRG2 P24 P25 P26 EXI6 EXTRG6 P27 EXI7 EXTRG7 P32 P33 V DD V SS V DDL RESET_N P00 TES...

Page 42: ...ML62Q1000 Group User s Manual Chapter 1 Overview FEUL62Q1000 1 25 1 3 1 7 ML62Q1530 1531 1532 1533 1534 48pin TQFP Figure 1 13 ML62Q1530 1531 1532 1533 1534 48pin TQFP...

Page 43: ...ML62Q1000 Group User s Manual Chapter 1 Overview FEUL62Q1000 1 26 1 3 1 8 ML62Q1540 1541 1542 1543 1544 52pin TQFP Figure 1 14 ML62Q1540 1541 1542 1543 1544 52pin TQFP...

Page 44: ...2Q1000 Group User s Manual Chapter 1 Overview FEUL62Q1000 1 27 1 3 1 9 ML62Q1550 1551 1552 1553 1554 1555 1556 1557 64pin TQFP QFP Figure 1 15 ML62Q1550 1551 1552 1553 1554 1555 1556 1557 64pin TQFP Q...

Page 45: ...P82 P44 DACOUT1 P45 P02 EXI0 EXTRG0 P03 EXI1 EXTRG1 P46 P47 P76 EXI10 P75 P74 20 P73 21 P72 P71 P70 P04 EXI2 EXTRG2 P05 P06 P07 P10 P11 P12 P13 P50 EXI8 P51 P52 P53 P93 P94 P95 P96 40 NC 41 V DD P54 P...

Page 46: ...2 EXI0 EXTRG0 P03 EXI1 EXTRG1 P46 P47 P76 EXI10 P75 P74 25 P73 26 P72 P71 P70 P04 EXI2 EXTRG2 P05 P06 P07 P10 P11 P12 P13 P50 EXI8 P51 P52 P53 P90 P91 P92 P93 P94 P95 P96 P97 PA0 50 NC 51 V DD PA1 PA2...

Page 47: ...P45 P02 EXI0 EXTRG0 P03 EXI1 EXTRG1 P46 P47 P76 EXI10 P75 P74 P73 P72 P71 30 P70 31 P04 EXI2 EXTRG2 P05 P06 P07 P10 P11 P12 P13 P50 EXI8 P51 P52 P53 P90 P91 P92 P93 P94 P95 P96 50 P97 51 PA0 NC V DD...

Page 48: ...ML62Q1000 Group User s Manual Chapter 1 Overview FEUL62Q1000 1 31 1 3 1 13 ML62Q1700 1701 1702 1703 1704 48pin TQFP Figure 1 19 ML62Q1700 1701 1702 1703 1704 48pin TQFP...

Page 49: ...ML62Q1000 Group User s Manual Chapter 1 Overview FEUL62Q1000 1 32 1 3 1 14 ML62Q1710 1711 1712 1713 1714 52pin TQFP Figure 1 20 ML62Q1710 1711 1712 1713 1714 52pin TQFP...

Page 50: ...p User s Manual Chapter 1 Overview FEUL62Q1000 1 33 1 3 1 15 ML62Q1720 1721 1722 1723 1724 1725 1726 1727 64pin TQFP QFP Figure 1 21 ML62Q1720 1721 1722 1723 1724 1725 1726 1727 64pin TQFP QFP TOP VIE...

Page 51: ...EG1 P11 COM5 SEG2 P12 COM6 SEG3 P13 COM7 SEG4 P50 EXI8 SEG5 P51 SEG6 P52 SEG7 P53 SEG8 P93 SEG12 P94 SEG13 P95 SEG14 P96 SEG15 40 NC 41 V DD P54 SEG20 P55 SEG21 P14 SEG22 P15 SEG23 P16 SEG24 P17 EXI3...

Page 52: ...6 P52 SEG7 P53 SEG8 P90 SEG9 P91 SEG10 P92 SEG11 P93 SEG12 P94 SEG13 P95 SEG14 P96 SEG15 P97 SEG16 PA0 SEG17 50 NC 51 V DD PA1 SEG18 PA2 SEG19 P54 SEG20 P55 SEG21 P14 SEG22 P15 SEG23 P16 SEG24 P17 EXI...

Page 53: ...I8 SEG5 P51 SEG6 P52 SEG7 P53 SEG8 P90 SEG9 P91 SEG10 P92 SEG11 P93 SEG12 P94 SEG13 P95 SEG14 P96 SEG15 50 P97 SEG16 51 PA0 SEG17 NC V DD PA1 SEG18 PA2 SEG19 P54 SEG20 P55 SEG21 P14 SEG22 P15 SEG23 P1...

Page 54: ...erter 0 output pin 2 nd function 3 rd function 4 th function 5 th function 6 th function 7 th function 8 th function 6 5 3 7 7 P02 EXI0 EXTRG0 I O General I O pin External interrupt Functional timer e...

Page 55: ...I O General I O pin 2 nd function SU0_TXD1 3 rd function 4 th function 5 th function 6 th function 7 th function 8 th function 14 P11 I O General I O pin 2 nd function SU0_SCLK 3 rd function 4 th fun...

Page 56: ...1P 6 th function 7 th function BZ0P 8 th function AIN0 11 10 9 15 21 P20 I O General I O pin 2 nd function SU0_TXD1 3 rd function 4 th function 5 th function FTM1N 6 th function TBCOUT1 7 th function...

Page 57: ...5 14 15 21 27 P26 EXI6 EXTRG6 I O General I O pin External interrupt Functional timer external trigger 2 nd function SU1_RXD1 3 rd function SU1_RXD0 4 th function I2CU0_SDA 5 th function FTM3P 6 th fu...

Page 58: ...QFN 32Pin No TQFP WQFN Pn name Primary function Shared function 23 31 P32 I O General I O pin 2 nd function SU1_RXD1 3 rd function SU1_RXD0 4 th function 5 th function 6 th function 7 th function 8 th...

Page 59: ...resonator connection pin 2 2 2 2 2 4 XT1 PI01 I General Input pin Low speed crystal resonator connection pin 7 7 7 7 7 9 P00 TEST0 I O General I O pin Used for on chip debug interface Unavailable to u...

Page 60: ...SU0_SCLK 3 rd function 4 th functiion I2CU0_SCL 5 th function TMH0OUT 6 th function 7 th function 8 th function 17 18 22 26 31 33 P05 I O General I O pin 2 nd function 3 rd function 4 th functiion 5...

Page 61: ...function 6 th function 7 th function 8 th function 21 22 26 30 35 37 P11 I O General I O pin 2 nd function SU0_SCLK 3 rd function 4 th functiion 5 th function 6 th function 7 th function 8 th function...

Page 62: ...th function 26 28 36 46 58 60 P15 I O General I O pin 2 nd function 3 rd function 4 th functiion I2CU0_SDA 5 th function 6 th function 7 th function 8 th function 27 29 37 47 59 61 P16 I O General I O...

Page 63: ...nterrupt 4 Functional timer external trigger 2 nd function SU1_RXD0 SU1_SIN 3 rd function 4 th functiion 5 th function FTM2P 6 th function OUTLSCLK 7 th function 8 th function AIN2 31 33 41 51 63 65 P...

Page 64: ...O pin 2 nd function SU1_TXD0 SU1_SOUT 3 rd function SU1_TXD1 4 th functiion 5 th function 6 th function 7 th function 8 th function AIN5 35 37 45 55 67 69 P26 EXI6 EXTRG6 I O General I O pin External...

Page 65: ...on 5 th function 6 th function 7 th function 8 th function 38 42 52 68 85 87 P31 I O General I O pin 2 nd function 3 rd function 4 th functiion 5 th function 6 th function TBCOUT0 7 th function TBCOUT...

Page 66: ...unction 6 th function 7 th function 8 th function 40 50 66 83 85 P41 I O General I O pin 2 nd function 3 rd function 4 th functiion 5 th function 6 th function 7 th function 8 th function 63 79 96 98...

Page 67: ...tion SU4_RXD0 1 4 th functiion 5 th function 6 th function 7 th function 8 th function 10 13 18 20 P45 I O General I O pin 2 nd function SU4_TXD1 1 3 rd function 4 th functiion 5 th function 6 th func...

Page 68: ...nctiion 5 th function 6 th function 7 th function 8 th function 26 30 34 39 41 P51 I O General I O pin 2 nd function 3 rd function 4 th functiion 5 th function 6 th function 7 th function 8 th functio...

Page 69: ...th function 34 44 56 58 P55 I O General I O pin 2 nd function SU2_TXD1 3 rd function 4 th functiion 5 th function 6 th function 7 th function 8 th function 39 47 57 69 71 P56 I O General I O pin 2 nd...

Page 70: ...ctiion I2CM1_SCL 5 th function 6 th function 7 th function 8 th function 42 46 56 72 89 91 P61 I O General I O pin 2 nd function 3 rd function 4 th functiion I2CM1_SDA 5 th function 6 th function 7 th...

Page 71: ...0 76 93 95 P65 I O General I O pin 2 nd function SU3_TXD0 SU3_SOUT 1 2 3 3 rd function SU3_TXD1 1 2 3 4 th functiion 5 th function FTM5N 6 th function 7 th function 8 th function AIN8 47 51 61 77 94 9...

Page 72: ...function TMH6OUT 1 6 th function 7 th function 8 th function 15 16 19 23 28 30 P71 I O General I O pin 2 nd function 3 rd function 4 th functiion 5 th function 6 th function 7 th function 8 th functi...

Page 73: ...d function 4 th functiion 5 th function 6 th function 7 th function 8 th function 11 12 15 19 24 26 P75 I O General I O pin 2 nd function 3 rd function 4 th functiion 5 th function 6 th function 7 th...

Page 74: ...3 rd function 4 th functiion 5 th function 6 th function 7 th function 8 th function 10 10 12 P81 I O General I O pin 2 nd function SU4_TXD0 SU4_SOUT 3 rd function SU4_TXD1 4 th functiion 5 th functio...

Page 75: ...nd function 3 rd function 4 th functiion 5 th function 6 th function 7 th function 8 th function 14 16 P85 I O General I O pin 2 nd function 3 rd function 4 th functiion 5 th function 6 th function 7...

Page 76: ...rd function 4 th functiion 5 th function 6 th function 7 th function 8 th function 43 45 P91 I O General I O pin 2 nd function 3 rd function 4 th functiion 5 th function 6 th function 7 th function 8...

Page 77: ...U4_SOUT 3 rd function SU4_TXD1 4 th functiion 5 th function FTM6N 6 th function 7 th function 8 th function 39 47 49 P95 I O General I O pin 2 nd function SU4_SCLK 3 rd function 4 th functiion 5 th fu...

Page 78: ...4 th functiion 5 th function 6 th function 7 th function 8 th function 53 55 PA1 I O General I O pin 2 nd function 3 rd function 4 th functiion 5 th function 6 th function 7 th function 8 th function...

Page 79: ...unction 3 rd function 4 th functiion 5 th function FTM7N 6 th function 7 th function 8 th function AIN15 73 75 PA5 I O General I O pin 2 nd function 3 rd function 4 th functiion 5 th function 6 th fun...

Page 80: ...4 th functiion 5 th function 6 th function 7 th function 8 th function 77 79 PB1 I O General I O pin 2 nd function 3 rd function 4 th functiion 5 th function 6 th function 7 th function 8 th function...

Page 81: ...5_SCLK 3 rd function 4 th functiion 5 th function 6 th function 7 th function 8 th function 64 81 83 PB5 I O General I O pin 2 nd function SU5_RXD1 3 rd function SU5_RXD0 4 th functiion 5 th function...

Page 82: ...crystal resonator connection pin 2 2 2 2 2 4 XT1 PI01 I General Input pin Low speed crystal resonator connection pin 7 7 7 7 7 9 P00 TEST0 I O General I O pin Used for on chip debug interface Unavail...

Page 83: ...CU0_SCL 5 th function TMH0OUT 6 th function 7 th function 8 th function 17 18 22 26 31 33 P05 COM1 I O General I O pin LCD Common output pin 2 nd function 3 rd function 4 th functiion 5 th function 6...

Page 84: ...2 26 30 35 37 P11 COM5 SEG2 I O General I O pin LCD Common output pin LCD Segment output pin 2 nd function SU0_SCLK 3 rd function 4 th functiion 5 th function 6 th function 7 th function 8 th function...

Page 85: ...P15 SEG23 I O General I O pin LCD Segment output pin 2 nd function 3 rd function 4 th functiion I2CU0_SDA 5 th function 6 th function 7 th function 8 th function 27 29 37 47 59 61 P16 SEG24 I O Gener...

Page 86: ...External interrupt 4 Functional timer external trigger LCD Segment output pin 2 nd function SU1_RXD0 SU1_SIN 3 rd function 4 th functiion 5 th function FTM2P 6 th function OUTLSCLK 7 th function 8 th...

Page 87: ...put pin 2 nd function SU1_TXD0 SU1_SOUT 3 rd function SU1_TXD1 4 th functiion 5 th function 6 th function 7 th function 8 th function AIN5 35 37 45 55 67 69 P26 EXI6 EXTRG6 SEG32 I O General I O pin E...

Page 88: ...on 7 th function 8 th function 38 42 52 68 85 87 P31 SEG50 I O General I O pin LCD Segment output pin 2 nd function 3 rd function 4 th functiion 5 th function 6 th function TBCOUT0 7 th function TBCOU...

Page 89: ...nction 7 th function 8 th function 40 50 66 83 85 P41 SEG48 I O General I O pin LCD Segment output pin 2 nd function 3 rd function 4 th functiion 5 th function 6 th function 7 th function 8 th functio...

Page 90: ...N 6 th function 7 th function 8 th function 10 13 18 20 P45 I O General I O pin 2 nd function SU4_TXD1 1 3 rd function 4 th functiion 5 th function 6 th function 7 th function 8 th function 13 16 21 2...

Page 91: ...unction 7 th function 8 th function 26 30 34 39 41 P51 SEG6 I O General I O pin LCD Segment output pin 2 nd function 3 rd function 4 th functiion 5 th function 6 th function 7 th function 8 th functio...

Page 92: ...EG21 I O General I O pin LCD Segment output pin 2 nd function SU2_TXD1 3 rd function 4 th functiion 5 th function 6 th function 7 th function 8 th function 39 47 57 69 71 P56 SEG34 I O General I O pin...

Page 93: ...n 6 th function 7 th function 8 th function 42 46 56 72 89 91 P61 SEG54 I O General I O pin LCD Segment output pin 2 nd function 3 rd function 4 th functiion I2CM1_SDA 5 th function 6 th function 7 th...

Page 94: ...ral I O pin LCD Segment output pin 2 nd function SU3_TXD0 SU3_SOUT 1 2 3 3 rd function SU3_TXD1 1 2 3 4 th functiion 5 th function FTM5N 6 th function 7 th function 8 th function AIN8 47 51 61 77 94 9...

Page 95: ...r source 3 14 15 18 22 27 29 VL2 LCD bias power source 2 13 14 17 21 26 28 VL1 LCD bias power source 1 12 13 16 20 25 27 C2 LCD bias power source generation capacitor connection pin 2 11 12 15 19 24 2...

Page 96: ...function 4 th functiion 5 th function 6 th function 7 th function 8 th function 10 10 12 P81 I O General I O pin 2 nd function SU4_TXD0 SU4_SOUT 3 rd function SU4_TXD1 4 th functiion 5 th function 6...

Page 97: ..._TXD0 3 rd function SU5_TXD01 4 th functiion 5 th function 6 th function 7 th function 8 th function 14 16 P85 I O General I O pin 2 nd function 3 rd function 4 th functiion 5 th function 6 th functio...

Page 98: ...th function 6 th function 7 th function 8 th function 43 45 P91 SEG10 I O General I O pin LCD Segment output pin 2 nd function 3 rd function 4 th functiion 5 th function 6 th function 7 th function 8...

Page 99: ...1 4 th functiion 5 th function FTM6N 6 th function 7 th function 8 th function 39 47 49 P95 SEG14 I O General I O pin LCD Segment output pin 2 nd function SU4_SCLK 3 rd function 4 th functiion 5 th fu...

Page 100: ...6 th function 7 th function 8 th function 53 55 PA1 SEG18 I O General I O pin LCD Segment output pin 2 nd function 3 rd function 4 th functiion 5 th function 6 th function 7 th function 8 th function...

Page 101: ...nctiion 5 th function FTM7N 6 th function 7 th function 8 th function AIN15 73 75 PA5 SEG38 I O General I O pin LCD Segment output pin 2 nd function 3 rd function 4 th functiion 5 th function 6 th fun...

Page 102: ...6 th function 7 th function 8 th function 77 79 PB1 SEG42 I O General I O pin LCD Segment output pin 2 nd function 3 rd function 4 th functiion 5 th function 6 th function 7 th function 8 th function...

Page 103: ...ctiion 5 th function 6 th function 7 th function 8 th function 64 81 83 PB5 SEG46 I O General I O pin LCD Segment output pin 2 nd function SU5_RXD1 3 rd function SU5_RXD0 4 th functiion 5 th function...

Page 104: ...lled Negative XT0 XT0 I Low speed crystal oscillation pins Conenct 32 768kHz crystal resonator and have capacitors between the pin and VSS XT1 XT1 O OUTLSCLK P02 O Low speed clock output P21 OUTHSCLK...

Page 105: ...communication unit2 UART0 data input pin Positive P56 SU2_TXD1 P55 O Serial communication unit2 UART1 data output pin Positive P57 SU2_RXD1 P54 I Serial communication unit2 UART1 data input pin Posit...

Page 106: ...clock I O pin Positive SU3_SOUT P65 O Serial communication unit3 Synchronous serial data output pin Positive SU4_SIN P80 I Serial communication unit4 Synchronous serial data input pin Positive P93 SU...

Page 107: ...EXTRG1 P03 I 16bit Functional Timer event trigger input pin EXTRG2 P04 I 16bit Functional Timer event trigger input pin EXTRG3 P17 I 16bit Functional Timer event trigger input pin EXTRG4 P21 I 16bit F...

Page 108: ...SA type A D converter channel 1 input pin AIN2 P21 I SA type A D converter channel 2 input pin AIN3 P22 I SA type A D converter channel 3 input pin AIN4 P24 I SA type A D converter channel 4 input pi...

Page 109: ...ment output pin SEG14 P95 Segment output pin SEG15 P96 Segment output pin SEG16 P97 Segment output pin SEG17 PA0 Segment output pin SEG18 PA1 Segment output pin SEG19 PA2 Segment output pin SEG20 P54...

Page 110: ...n SEG52 P33 Segment output pin SEG53 P60 Segment output pin SEG54 P61 Segment output pin SEG55 P62 Segment output pin SEG56 P63 Segment output pin SEG57 P64 Segment output pin SEG58 P65 Segment output...

Page 111: ...pins with the initial condition of Hi impedance mode P01 to P07 P10 to P17 P20 to P27 P30 to P33 P40 to P47 P50 to P57 P60 to P67 P70 P76 P77 P80 to P87 P90 to P97 PA0 to PA7 PB0 to PB7 C1 C2 OPEN VL...

Page 112: ...Chapter 2 CPU and Memory Space...

Page 113: ...Product name Program memory space Data memory space Data flash size Memory model ROM size RAM size ML62Q1323 ML62Q1333 16 Kbyte 2 Kbyte 2 Kbyte SMALL ML62Q1324 ML62Q1334 24 Kbyte ML62Q1325 ML62Q1335...

Page 114: ...e RAM size ML62Q1700 ML62Q1710 ML62Q1720 32 Kbyte 8 Kbyte 4 Kbyte SMALL ML62Q1701 ML62Q1711 ML62Q1721 48 Kbyte ML62Q1702 ML62Q1712 ML62Q1722 64 Kbyte ML62Q1703 ML62Q1713 ML62Q1723 96 Kbytes 8 Kbyte LA...

Page 115: ...erations branches conditional branches call return stack manipulation and arithmetic shifts Variety of addressing modes Register addressing Register indirect addressing Stack pointer addressing Contro...

Page 116: ...n codes read from the program memory are stored into the built in buffer The CPU can work at high speed to read the instructions from the buffer In contiguous address instruction processing the instru...

Page 117: ...peration time 4 cycles Division 32 bit 16 bit operation time 8 cycles Division 32 bit 32 bit operation time 16 cycles Multiply accumulate non saturating 16 bit x 16 bit 32 bit operation time 4 cycles...

Page 118: ...R W 0x00 C register L CR4 CER4 CXR4 R W 0x00 C register H CR5 R W 0x00 D register L CR6 CER6 R W 0x00 D register H CR7 R W 0x00 Operation mode register CR8 CER8 CXR8 CQR8 R W 0x00 Operation status re...

Page 119: ...R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word CER2 Byte CR3 CR2 Bit breg15 breg14 breg13 breg12 breg11 breg10 breg9 breg8 breg7 breg6 breg5 breg4...

Page 120: ...d symbol CQR0 Double word symbol CXR4 CXR0 Word symbol CER6 CER4 CER2 CER0 Byte symbol CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 Multiplication 16 bit x 16 bit Input Multiplicand 15 0 Multiplier 15 0 Result Pro...

Page 121: ...ach operation In addition a value can be written 14 z This becomes 1 if the operation result is 0 The value is updated in each operation In addition a value can be written 13 s This becomes 1 if the o...

Page 122: ...each operation mode Value set to CR8 Signed Unsigned Multiplication 16 bit x 16 bit initial value 0x90 0x80 Division 32 bit 16 bit 0x91 0x81 Division 32 bit 32 bit 0x95 0x85 Multiply accumulate non s...

Page 123: ...the consecutive registers The bit symbol are unavailable to use in the software Access R Access size 8 16 bits Initial value 0x8100 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word CER14 Byte CR15 CR14 Bit...

Page 124: ...mprovement in access speed because it is not required to specify DSR of the data memory space In addition the mirror area is provided to read program memory space segments 0 to 7 through a memory acce...

Page 125: ...2 to 2 14 show the program memory space configuration of each product of the ML620Q1000 series n ML62Q1300 group CSR PC Segment 0 CSR PC Segment 0 CSR PC Segment 0 0x0 0000 Vector table area or progr...

Page 126: ...or program code area 0x0 00FF 0x0 00FF 0x0 00FF 0x0 0100 Program code area 0x0 0100 Program code area 0x0 0100 Program code area 0x0 7FBF 0x0 7FC0 Code Option area 0x0 7FFF 64 byte 8 bit 0x0 BFBF ML62...

Page 127: ...4 byte 8 bit 0x0 FFFF 8 bit ML62Q1533 1543 1553 1563 1573 Size 96 Kbyte Figure 2 4 ML62Q1500 Group Configuration of Program Memory Space 2 CSR PC Segment 0 CSR PC Segment 1 0x0 0000 Vector table area...

Page 128: ...e 8 bit 0x0 FFFF 0x1 FFFF 8 bit 8 bit ML62Q1555 1565 1575 Size 160 Kbyte Figure 2 6 ML62Q1500 Group Configuration of Program Memory Space 4 CSR PC Segment 0 CSR PC Segment 1 CSR PC Segment 2 0x0 0000...

Page 129: ...0 0000 Vector table area or program code area 0xn 0000 n 1 2 Program code area 0x3 0000 Program code area 0x0 00FF 0x0 0100 Program code area 0x3 FFBF 0x3 FFC0 Code Option area 0x0 FFFF 0xn FFFF 0x3 F...

Page 130: ...program code area 0x0 00FF 0x0 00FF 0x0 00FF 0x0 0100 Program code area 0x0 0100 Program code area 0x0 0100 Program code area 0x0 7FBF 0x0 7FC0 Code Option area 0x0 7FFF 64 byte 8 bit 0x0 BFBF ML62Q1...

Page 131: ...byte 8 bit 0x0 FFFF 8 bit ML62Q1703 1713 1723 1733 1743 Size 96 Kbyte Figure 2 10 ML62Q1700 Group Configuration of Program Memory Space 2 CSR PC Segment 0 CSR PC Segment 1 0x0 0000 Vector table area...

Page 132: ...8 bit 0x0 FFFF 0x1 FFFF 8 bit 8 bit ML62Q1705 1715 1725 Size 160 Kbyte Figure 2 12 ML62Q1700 Group Configuration of Program Memory Space 4 CSR PC Segment 0 CSR PC Segment 1 CSR PC Segment 2 0x0 0000...

Page 133: ...ure 2 14 ML62Q1700 Group Configuration of Program Memory Space 6 Note The Code Option area 64 bytes is not available for the program code area For details of Code Option settings see Chapter 26 Code O...

Page 134: ...egment 0 DSR AR Segment 8 DSR AR Segment 31 0x00 0000 ROM window area 16 Kbyte 0x08 0000 Mirror area 16 Kbyte 0x1F 0000 Data flash area 2 Kbyte 0x1F 07FF 0x1F 0800 Unused area 0x00 3FFF 0x08 3FFF 0x00...

Page 135: ...00 SFR area 0x00 FFFF 0x08 FFFF 0x1F FFFF 8 bit 8 bit 8 bit ML62Q1325 1335 Figure 2 17 ML62Q1300 Group Configuration of Data Memory Space 3 DSR AR Segment 0 DSR AR Segment 8 DSR AR Segment 31 0x00 000...

Page 136: ...8 bit 8 bit 8 bit ML62Q1346 1366 Figure 2 19 ML62Q1300 Group Configuration of Data Memory Space 5 DSR AR Segment 0 DSR AR Segment 1 0x00 0000 ROM window 0x01 0000 Test area area 1 Kbyte 56 Kbyte 0x01...

Page 137: ...0 F000 SFR area 0x00 FFFF 0x08 FFFF 0x1F FFFF 8 bit 8 bit 8 bit ML62Q1530 1540 1550 Figure 2 21 ML62Q1500 Group Configuration of Data Memory Space 1 DSR AR Segment 0 DSR AR Segment 8 DSR AR Segment 31...

Page 138: ...re 2 23 ML62Q1500 Group Configuration of Data Memory Space 3 DSR AR Segment 0 DSR AR Segment 1 0x00 0000 ROM window 0x01 0000 Mirror area area 32 Kbyte 52 Kbyte 0x01 7FFF 0x01 8000 Unused area 0x00 D0...

Page 139: ...e 0x09 8400 Unused area 0x08 FFFF 0x09 FFFF 0x1F FFFF 8 bit 8 bit 8 bit ML62Q1563 1573 Figure 2 25 ML62Q1500 Group Configuration of Data Memory Space 5 DSR AR Segment 0 DSR AR Segment 1 0x00 0000 ROM...

Page 140: ...igure 2 27 ML62Q1500 Group Configuration of Data Memory Space 7 DSR AR Segment 0 DSR AR Segment 1 DSR AR Segment 2 0x00 0000 ROM window 0x01 0000 Mirror area 0x02 0000 Mirror area area 64 Kbyte 32 Kby...

Page 141: ...to A FFFF 0x0B FFFF 0x1F FFFF 8 bit 8 bit 8 bit 8 bit ML62Q1556 1566 1576 Figure 2 29 ML62Q1500 Group Configuration of Data Memory Space 9 DSR AR Segment 0 DSR AR Segments 1 to 3 0x00 0000 ROM window...

Page 142: ...0 F000 SFR area 0x00 FFFF 0x08 FFFF 0x1F FFFF 8 bit 8 bit 8 bit ML62Q1700 1710 1720 Figure 2 31 ML62Q1700 Group Configuration of Data Memory Space 1 DSR AR Segment 0 DSR AR Segment 8 DSR AR Segment 31...

Page 143: ...re 2 33 ML62Q1700 Group Configuration of Data Memory Space 3 DSR AR Segment 0 DSR AR Segment 1 0x00 0000 ROM window 0x01 0000 Mirror area area 32 Kbyte 52 Kbyte 0x01 7FFF 0x01 8000 Unused area 0x00 D0...

Page 144: ...e 0x09 8400 Unused area 0x08 FFFF 0x09 FFFF 0x1F FFFF 8 bit 8 bit 8 bit ML62Q1733 1743 Figure 2 35 ML62Q1700 Group Configuration of Data Memory Space 5 DSR AR Segment 0 DSR AR Segment 1 0x00 0000 ROM...

Page 145: ...igure 2 37 ML62Q1700 Group Configuration of Data Memory Space 7 DSR AR Segment 0 DSR AR Segment 1 DSR AR Segment 2 0x00 0000 ROM window 0x01 0000 Mirror area 0x02 0000 Mirror area area 64 Kbyte 32 Kby...

Page 146: ...to A FFFF 0x0B FFFF 0x1F FFFF 8 bit 8 bit 8 bit 8 bit ML62Q1726 1736 1746 Figure 2 39 ML62Q1700 Group Configuration of Data Memory Space 9 DSR AR Segment 0 DSR AR Segments 1 to 3 0x00 0000 ROM window...

Page 147: ...o prevent the CPU works incorrectly The segment 0 of program memory space and the segment of data memory space are in different space but the segment 0 of program memory space is readable through the...

Page 148: ...and Memory Space FEUL62Q1000 2 36 2 7 Description of Registers List of Registers 2 7 1 Address Name Symbol name R W Size Initial value Byte Word 0xF000 Data segment register DSR R W 8 0x00 0xF0A0 Flas...

Page 149: ...ment 2 00011 Mirror area of code segment 3 00100 Mirror area of code segment 4 00101 Mirror area of code segment 5 00110 Mirror area of code segment 6 00111 Mirror area of code segment 7 01000 Data se...

Page 150: ...0 0 0 0 0 0 0 Bit No Bit symbol name Description 5 to 4 RES1 to RES0 Bits to set the code segment of the area to remap For example when writing 0x1 to RES1 0 and 0xF to REA15 12 then remapping them t...

Page 151: ...The remap function and IAP In Application Programming program enable your application to reprogram the firmware Two ways are available to start the remap function 1 Software Remap Start remapping by r...

Page 152: ...how to use the remapping function Refer to ML62Q1000 Series IAP Sample Program for how to re write the user application program on the flash memory using the remapping function Software Remap 2 8 2 Th...

Page 153: ...itialized by the CPU reset BRK instruction and the remap starts at the updated address The REMAPADD register is initialized by the system reset RESETN pin reset VLS reset WDT reset and unused ROM area...

Page 154: ...Chapter 3 Reset Function...

Page 155: ...put pin reset This chapter Power On Reset POR This chapter Reset by watchdog timer WDT overflow Chapter 10 Watchdog Timer Reset by watchdog timer WDT invalid clear operation Chapter 10 Watchdog Timer...

Page 156: ...ing on its cause as this function contains following features to identify the cause in an early stage Reset status register RSTAT to indicate the cause of the reset Reset status register SRSTAT to ind...

Page 157: ...OFTRCON Software reset control register Other circuits Power supply and oscillation circuits start control part etc Figure 3 1 Configuration of Reset Generation Circuit Power on reset Reset signal to...

Page 158: ...ML62Q1000 Series User s Manual Chapter 3 Reset Function FEUL62Q1000 3 4 3 1 3List of Pins Pin name I O Function RESET_N I Reset input pin...

Page 159: ...5 3 2 Description of Registers 3 2 1List of Registers Address Name Symbol name R W Size Initial value Byte Word 0xF058 Reset status register RSTATL RSTAT R W 8 16 Undefined 0xF059 RSTATH R W 8 Undefin...

Page 160: ...ten 0 No CPU reset through the BRK instruction occurred 1 CPU reset by BRK instruction occurred 7 INITE A read only bit to indicate that an abnormality occurred in starting LSI If this bit is set to 1...

Page 161: ...Chapter 3 Reset Function FEUL62Q1000 3 7 Bit No Bit symbol name Description 0 POR A bit to indicate that a power on reset has occurred This bit is reset to 0 when 1 is written 0 No power on reset occu...

Page 162: ...9 Safety Function for details of the safety function Address 0xF05A SRSTAT Access R W Access size 8 bit Initial value Undefined 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word Byte SRSTAT Bit RPER FIAR R W...

Page 163: ...eset SOFTRCON reset Reset available Reset unavailable Hardware Power circuit oscillation circuit start control part code option control part etc Note The voltage level supervisor function is only init...

Page 164: ...y are set to the stack pointer SP The contents of addresses 0x0002 0x0003 in segment 0 of the program memory are set to the program counter PC 4 The transition to the program run mode takes place when...

Page 165: ...begins to run the program with low speed clock LSCLK at approximately 32 768kHz If switching the CPU to a high speed clock start the voltage level supervisor VLS function and perform one of the follow...

Page 166: ...Chapter 4 Power Management...

Page 167: ...CPU and peripherals continue to work HALT H mode Stop the CPU peripherals continue to work with low speed clock only forcely stop high speed clock and restart the high speed clcok after releasing the...

Page 168: ...qualifies for entering STOP mode and STOP D mode Data of RAM and SFR are retained even in the STOP D mode Clock supply is control able peripheral by peripheral to reduce the current consumption by bl...

Page 169: ...symbols in the figure are assigned to the standby control register SBYCON Figure 4 1 Operating State Transition Diagram System reset Mode Reset or BRK instruction Reset released Program operation Mod...

Page 170: ...ock clock control register 0 BCKCON0L BCKCON0 R W 8 16 0x00 0xF071 BCKCON0H R W 8 0x00 0xF072 Block clock control register 1 BCKCON1L BCKCON1 R W 8 16 0x00 0xF073 BCKCON1H R W 8 0x00 0xF074 Block cloc...

Page 171: ...ecify the registers Description 1 Write 0x5n and 0xAn n arbitrary in 0 F in sequence into STPACP register Enables to enter the STOP mode or STOP D mode only once 2 Set STP bit or STPD bit of SBYCON re...

Page 172: ...is allowed by using STPACP the operating state enters the STOP mode When an external interrupt enabled in the interrupt enable registers IE0 to IE7 is generated the STOP mode gets canceled and return...

Page 173: ...W W W W W W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 How to reset collectively the peripheral circuits Procedure How to specify the registers Description 1 Write 0x3n and 0xCn n arbitrary in 0 F...

Page 174: ...R R R R R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit symbol name Description 7 1 Reserved bit 0 SOFTR SOFTR is a bit to reset collectively the all peripheral circuits belong to the BRE...

Page 175: ...ng the clock to the peripheral circuit 5 DCKTM5 This bit controls the clock supply for the peripheral circuit of 16bit Timer 5 0 Enable supplying the clock to the peripheral circuit initial value 1 St...

Page 176: ...for the peripheral circuit of I 2 C Bus Master 1 0 Enable supplying the clock to the peripheral circuit initial value 1 Stop supplying the clock to the peripheral circuit 8 DCKI2CM0 This bit controls...

Page 177: ...circuit of Functional Timer 2 0 Enable supplying the clock to the peripheral circuit initial value 1 Stop supplying the clock to the peripheral circuit 0 DCKFTM0 This bit controls the clock supply for...

Page 178: ...s bit controls the clock supply for the peripheral circuit of Multiplier Divider 0 Enable supplying the clock to the peripheral circuit initial value 1 Stop supplying the clock to the peripheral circu...

Page 179: ...it initial value 1 Stop supplying the clock to the peripheral circuit Note The DCKACC bit can be set to 1 when the multiplication division library muldivu8 lib is not specified in the target option of...

Page 180: ...pheral circuit 4 DCKCMP0 This bit controls the clock supply for the peripheral circuit of Analog Comparator 0 0 Enable supplying the clock to the peripheral circuit initial value 1 Stop supplying the...

Page 181: ...value 1 Remain to reset the peripheral circuit 5 RSETM5 This bit controls to reset the peripheral circuit of 16bit Timer 5 0 Cancel to reset the peripheral circuit initial value 1 Remain to reset the...

Page 182: ...el to reset the peripheral circuit initial value 1 Remain to reset the peripheral circuit 8 RSEI2CM0 This bit controls to reset the peripheral circuit of I 2 C Bus Master 0 0 Cancel to reset the perip...

Page 183: ...ue 1 Remain to reset the peripheral circuit 0 RSEFTM0 This bit controls to reset the peripheral circuit of Functional Timer 0 0 Cancel to reset the peripheral circuit initial value 1 Remain to reset t...

Page 184: ...r 0 Cancel to reset the peripheral circuit initial value 1 Remain to reset the peripheral circuit 12 Reserved bit 11 RSECRC This bit controls to reset the peripheral circuit of CRC calculator 0 Cancel...

Page 185: ...division library muldivu8 lib is not specified in the target option of the Integrated Development Environment IDEU8 To restart the operation of the peripheral circuits reset them at first by the bloc...

Page 186: ...he peripheral circuit 4 RSECMP0 This bit controls to reset the peripheral circuit of Analog Comparator 0 0 Cancel to reset the peripheral circuit initial value 1 Remain to reset the peripheral circuit...

Page 187: ...n with previous clock condition LSCLK or HSCLK for the system clock SYSTEMCLK chosen before entering the HALT mode See 4 3 7 Operation of Each Function in Standby Mode for the operation of each functi...

Page 188: ...released at the rising edge of the next SYSTEMCLK HSCLK is forcibly enabled and the mode shifts back to the program run mode with the SYSTEMCLK in the HSCLK state Even if the high speed oscillation i...

Page 189: ...un mode with the SYSTEMCLK chosen before entering the STOP mode Figure 4 4 shows STOP mode operation waveforms of the low speed oscillation circuit Figure 4 5 shows STOP mode operation waveforms of th...

Page 190: ...ltage level supervisor VLS or interrupt requests from the analog comparator It returns to the program run mode with the SYSTEMCLK chosen before entering the STOP D mode Figure 4 6 shows the STOP D mod...

Page 191: ...ram operation does not go to the interrupt routine 2 3 1 1 1 0 1 1 1 1 After returning from the standby mode the program operation restarts from the instruction next to the instruction that enters the...

Page 192: ...ltiplier Divider Crystal oscillation circuit 7 Simplified RTC 7 LCD driver 8 Operable Not operable stop 1 If a sampling function is selected it is forcibly disabled 2 In the case of transition to the...

Page 193: ...gh speed CPU clock TRTPLL Approximately 320 s Approximately 305 s STOP D mode Low speed CPU clock TRTLS Approximately 320 s Approximately 305 s High speed CPU clock TRTPLL Approximately 320 s Approxim...

Page 194: ...TM3 RSEFTM3 Functional timer 4 DCKFTM4 RSEFTM4 Functional timer 5 DCKFTM5 RSEFTM5 Functional timer 6 DCKFTM6 RSEFTM6 Functional timer 7 DCKFTM7 RSEFTM7 I 2 C bus master 0 DCKI2CM0 RSEI2CM0 I 2 C bus m...

Page 195: ...ependent of the product specification Table 4 7 Availability of the SFR bit symbols in BCLCONn register and BRECONn register Control register bit Available Unavailable Word symbol Bit symbol Word symb...

Page 196: ...Chapter 5 Interrupts...

Page 197: ...terrupts and the software interrupt Master Interrupt Enable MIE flag enables or disables collectively the all maskable interrupts For more details about MIE see nX U16 100 Core Instruction Manual Each...

Page 198: ...request register 67 IRQ6 IRQ67 R W 8 16 0x00 0xF02F IRQ7 R W 8 0x00 0xF030 Interrupt level control enable register ILEN R W 8 0x00 0xF031 Reserved R 8 0x00 0xF032 Current interrupt level management re...

Page 199: ...Interrupt DMACINT IRQ2 2 IE2 2 ILC2 5 4 MCU Status Interrupt MCSINT IRQ2 3 IE2 3 ILC2 7 6 Serial Communication Unit 00 Interrupt SIU00INT IRQ2 4 IE2 4 ILC2 9 8 Serial Communication Unit 01 Interrupt...

Page 200: ...5INT IRQ6 0 IE6 0 ILC6 1 0 Serial Communication Unit 30 Interrupt SIU30INT IRQ6 1 IE6 1 ILC6 3 2 Serial Communication Unit 31 Interrupt SIU31INT IRQ6 2 IE6 2 ILC6 5 4 Serial Communication Unit 40 Inte...

Page 201: ...s bit controls to enable or disable the external pin interrupt 6 EXI6INT 0 Disable the interrupt initial value 1 Enable the interrupt 13 EPI5 This bit controls to enable or disable the external pin in...

Page 202: ...the interrupt initial value 1 Enable the interrupt 14 ETM0 This bit controls to enable or disable the 16bit Timer 0 interrupt TM0INT 0 Disable the interrupt initial value 1 Enable the interrupt 13 EF...

Page 203: ...terrupt initial value 1 Enable the interrupt 2 EMCS This bit controls to enable or disable the MCU Status interrupt 1 MCSINT 0 Disable the interrupt initial value 1 Enable the interrupt 1 EDMA This bi...

Page 204: ...4 interrupt TM4INT 0 Disable the interrupt initial value 1 Enable the interrupt 13 EFTM5 This bit controls to enable or disable the Functional Timer 5 interrupt FTM5INT 0 Disable the interrupt initia...

Page 205: ...isable the interrupt initial value 1 Enable the interrupt 3 Reserved bit 2 ESIU11 This bit controls to enable or disable the Serial Communication unit 11 interrupt SIU11INT 0 Disable the interrupt ini...

Page 206: ...s bit controls to enable or disable the Low speed Time base counter 2 interrupt LTBC2INT 0 Disable the interrupt initial value 1 Enable the interrupt 12 ELTBC1 This bit controls to enable or disable t...

Page 207: ...1INT 0 Disable the interrupt initial value 1 Enable the interrupt 2 ESIU40 This bit controls to enable or disable the Serial Communication unit 40 interrupt SIU40INT 0 Disable the interrupt initial va...

Page 208: ...is accepted by the CPU Address 0xF028 IRQ0 IRQ01 0xF029 IRQ1 Access R W Access size 8 16bit Initial value 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word IRQ01 Byte IRQ1 IRQ0 Bit QPI7 QPI6 QPI5 QPI...

Page 209: ...EXI1INT 0 Not request the interrupt initial value 1 Request the interrupt 7 Reserved bit 6 QVLS0 This bit controls to request the VLS0 interrupt VLS0INT 0 Not request the interrupt initial value 1 Req...

Page 210: ...te IRQ3 IRQ2 Bit QTM1 QTM0 QFT M1 QFT M0 QI2C M1 QI2C M0 QEXT X QSA D QSIU 01 QSIU 00 QMC S QDM A QCB U R W R W R W R W R W R W R W R R W R R W R R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0...

Page 211: ...rols to request the Serial Communication unit 00 interrupt SIU00INT 0 Not request the interrupt initial value 1 Request the interrupt 2 QMCS This bit controls to request the MCU Status interrupt 1 MCS...

Page 212: ...TM2 QFT M3 QFT M2 QSIU 11 QSIU 10 QI2C U0 R W R W R W R W R W R W R W R W R W R W R W R W R W R R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit symbol name Description 15 QTM5 Thi...

Page 213: ...st the interrupt initial value 1 Request the interrupt 4 QFTM2 This bit controls to request the Functional Timer 2 interrupt FTM2INT 0 Not request the interrupt initial value 1 Request the interrupt 3...

Page 214: ...QLTB C0 QSIU 51 QSIU 50 QTM7 QTM6 QFT M7 QFT M6 QSIU 41 QSIU 40 QSIU 31 QSIU 30 R W R R W R W R W R R W R W R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bi...

Page 215: ...the interrupt initial value 1 Request the interrupt 3 QSIU41 This bit controls to request the Serial Communication unit 41 interrupt SIU41INT 0 Not request the interrupt initial value 1 Request the i...

Page 216: ...bit 0 ILE This bit controls to enable or disable the interrupt level control 0 Disable the interrupt initial value 1 Enable the interrupt Note Disable the interrupt level control function by resetting...

Page 217: ...al value 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word Byte CIL Bit CILN CILM 3 CILM 2 CILM 1 CILM 0 R W R R R R R R R R R W R R R R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit...

Page 218: ...0xF035 ILC01 Access R W Access size 8 16bit Initial value 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word ILC0 Byte ILC01 ILC00 Bit ILVL S0H ILVL S0L R W R R R W R W R R R R R R R R R R R R Initial...

Page 219: ...iption 15 14 ILPI7H ILPI7L This bit chooses the priority level of the External interrupt 7 EXI7INT 00 Level 1 Priority is lowest initial 01 Level 2 10 Level 3 11 Level 4 Priority is highest 13 12 ILPI...

Page 220: ...Level 2 10 Level 3 11 Level 4 Priority is highest 1 0 ILPI0H ILPI0L This bit chooses the priority level of the External interrupt 0 EXI0INT 00 Level 1 Priority is lowest initial 01 Level 2 10 Level 3...

Page 221: ...Bit symbol name Description 15 14 Reserved bit 13 12 ILSADH ILSADL This bit chooses the priority level of the Successive approximation type A D interrupt SADINT 00 Level 1 Priority is lowest initial 0...

Page 222: ...Level 1 Priority is lowest initial 01 Level 2 10 Level 3 11 Level 4 Priority is highest 1 See Chapter 29 Safety Function for more details 2 See Chapter 6 Clock Generation Circuit for more details Not...

Page 223: ...his bit chooses the priority level of the 16bit Timer 1 interrupt TM1INT 00 Level 1 Priority is lowest initial 01 Level 2 10 Level 3 11 Level 4 Priority is highest 13 12 ILTM0H ILTM0L This bit chooses...

Page 224: ...s the priority level of the External expanded interrupt EXTXINT 00 Level 1 Priority is lowest initial 01 Level 2 10 Level 3 11 Level 4 Priority is highest Note Write to this register when the interrup...

Page 225: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit symbol name Description 15 14 ILTM3H ILTM3L This bit chooses the priority level of the 16bit Timer 3 interrupt TM3INT 00 Level 1 Priority is lowest initial 01 L...

Page 226: ...ial 01 Level 2 10 Level 3 11 Level 4 Priority is highest 1 0 ILI2CU0H ILI2CU0L This bit chooses the priority level of the I 2 C Bus unit 0 interrupt I2CU0INT 00 Level 1 Priority is lowest initial 01 L...

Page 227: ...TM5H ILTM5L This bit chooses the priority level of the 16bit Timer 5 interrupt TM5INT 00 Level 1 Priority is lowest initial 01 Level 2 10 Level 3 11 Level 4 Priority is highest 13 12 ILTM4H ILTM4L Thi...

Page 228: ...ority is highest 1 0 ILSIU20H ILSIU20L 1 This bit chooses the priority level of the Serial Communication unit 20 interrupt SIU20INT 00 Level 1 Priority is lowest initial 01 Level 2 10 Level 3 11 Level...

Page 229: ...L This bit chooses the priority level of the 16bit Timer 7 interrupt TM7INT 00 Level 1 Priority is lowest initial 01 Level 2 10 Level 3 11 Level 4 Priority is highest 13 12 ILTM6H ILTM6L This bit choo...

Page 230: ...Level 2 10 Level 3 11 Level 4 Priority is highest 1 0 ILSIU30H ILSIU30L This bit chooses the priority level of the Serial Communication unit 30 interrupt SIU30INT 00 Level 1 Priority is lowest initia...

Page 231: ...ymbol name Description 15 14 Reserved bit 13 12 ILRTCH ILRTCL This bit chooses the priority level of the Simplified RTC interrupt RTCINT 00 Level 1 Priority is lowest initial 01 Level 2 10 Level 3 11...

Page 232: ...level of the Serial Communication unit 50 interrupt SIU50INT 00 Level 1 Priority is lowest initial 01 Level 2 10 Level 3 11 Level 4 Priority is highest Note Write to this register when the interrupt...

Page 233: ...f multiple interrupts are generated concurrently when the interrupt level control function is disabled they are processed starting from the interrupt with the highest priority with a smallest interrup...

Page 234: ...IU01INT 18 IRQ2 5 IE2 5 ILC2 11 10 0x002A Enabled 19 IRQ2 6 IE2 6 ILC2 13 12 0x002C Enabled Successive approximation type A D converter interrupt SADINT 20 IRQ2 7 IE2 7 ILC2 15 14 0x002E Enabled 21 IR...

Page 235: ...upt SIU40INT 48 IRQ6 3 IE6 3 ILC6 7 6 0x0066 Enabled Serial communication unit 41 interrupt SIU41INT 49 IRQ6 4 IE6 4 ILC6 9 8 0x0068 Enabled Functional timer 6 interrupt FTM6INT 50 IRQ6 5 IE6 5 ILC6 1...

Page 236: ...gram memory size is 64 Kbytes or less 3 Save PSW fin EPSW2 4 Set ELEVEL of PSW to 2 5 Set CSR to 0 not processed if the program memory size is 64 Kbytes or less 6 Transfer the value of the interrupt v...

Page 237: ...not called in an interrupt routine A 1 1 When multiple interrupts are disabled When the script is written in the assembly language Processing immediately after the start of interrupt routine execution...

Page 238: ...o return the contents of the stack to PC and PSW When the script is written in C Define the interrupt routine using the INTERRUPT pragma Specify 2 in the category field In this way appropriate codes a...

Page 239: ...e the interrupt routine using the INTERRUPT pragma Specify 1 in the category field In this way appropriate codes are produced through the C compiler CCU8 Example of description State A 2 1 For assembl...

Page 240: ...tten in C Define the interrupt routine using the INTERRUPT pragma Specify 2 in the category field In this way appropriate codes are produced through the C compiler CCU8 Example of description Status A...

Page 241: ...ecution Specify POP PSW PC to return the contents of the stack to PC and PSW When the script is written in C Define the interrupt routine using the INTERRUPT pragma Specify 2 in the category field In...

Page 242: ...aved data of EPSW to PSW and the saved data of LR to LR Description for C language Define the interrupt routine by using INTERRUPT pragma and specify 2 in the category field The C compiler CCU8 genera...

Page 243: ...are enabled Registers that should be saved in the stack are ELR2 and EPSW2 When programming in C it is not required to write program codes for saving restoring registers because they are generated in...

Page 244: ...ed in the interrupt function to disable multiple interrupts CCU8 displays an error After completion of the target interrupt processing it is necessary to write to the CIL register and clear the highes...

Page 245: ...Example of output _intr_fn_10 push lr ea push xr0 l r0 DSR push r0 func bl _func CIL 0 mov r0 00h st r0 0f022h pop r0 st r0 DSR pop xr0 pop ea lr rti When another function is called from an interrupt...

Page 246: ...le interrupts TM2msec _DI Disable multiple interrupts CIL 0 Clear the highest current interrupt request level If described as in the example intr_fn_20 is handled as an interrupt processing function t...

Page 247: ...cycle and the instruction at the beginning of the interrupt routine When the interrupt conditions are satisfied here an interrupt is generated immediately after the execution of the instruction at th...

Page 248: ...Chapter 6 Clock generation Circuit...

Page 249: ...oscillation circuit Adjustable to 1 by using the frequency adjustment function A crysatl resonator is connectable 1 In case the low speed crystal oscillaion stopped the clock is automatically switched...

Page 250: ...ck is unavailable on the ML62Q1300 group The XT0 XT1 pin do not exist 2 Available on the ML62Q1500 and ML62Q1700 group Figure 6 1 Configuration of Clock Generation Circuit Note After the power on or t...

Page 251: ...S 1 Simplified RTC LCD driver 3 The clock is supplied The clock is Not supplied 1 The clock is supplied for sampling 2 Available on the ML62Q1500 and ML62Q1700 group 3 Available on the ML62Q1700 group...

Page 252: ...007 Reserved R 8 0x00 0xF008 High speed clock wake up time setting register FHWUPT R W 8 0x00 0xF009 Reserved R 8 0x00 0xF00A Backup Control register 1 FBUCON R W 8 0x00 0xF00B Reserved R 8 0x00 0xF00...

Page 253: ...e HSCLK 001 1 2 HSCLK 010 1 4 HSCLK 011 1 8 HSCLK 100 1 16 HSCLK Initial value 101 1 32 HSCLK 110 Do not use 1 32 HSCLK 111 Do not use 1 32 HSCLK 11 Reserved bit 10 to 8 SYSC2 to SYSC0 These bits are...

Page 254: ...e of VDD is 1 6V VDD 1 8V set the system clock to 4 MHz or lower If it exceeds 4MHz the operation is not guaranteed For output of the high speed clock OUTHSCLK the output clock frequency is limited ac...

Page 255: ...y lowering the oscillation margin than the standard mode The tough mode increases the oscillation margin and heightens the resistance against leakage between the pins increases the current consumption...

Page 256: ...e read only attribute 0 The frequency of PLL oscillation is out of the target error or the PLL oscillation is stopped Initial value 1 The frequency of PLL oscillation is within the target error 6 to 2...

Page 257: ...alue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit symbol name Description 15 to 3 Reserved bit 2 1 rsvd Reserved bits Always write 0 to these bits 0 FHUT0 This bit is used to choose the wake up time of...

Page 258: ...bit 0 LOSCB This bit is used to switch the backup clock The bit is automatically set to 1 when LOSCM 1 0 bits of Low speed Clock Mode Register FLMOD is set to 0x01 Write 1 to this bit to switch the lo...

Page 259: ...he LOSCS is 1 when the low speed crystal oscillation clock is stopped or in STOP STOP D mode LOSCS changes from 0 to 1 on the following conditions 1 When the CPU enters STOP STOP D mode When releasing...

Page 260: ...R W R R R R R R R R W W W W W W W W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit symbol name Description 15 to 8 Reserved bit 7 to 0 OSCBACP7 to OSCBACP0 These bits are used to prevent err...

Page 261: ...10 9 8 7 6 5 4 3 2 1 0 Word Byte FBTCON Bit LOS CL LOS CT R W R R R R R R R R R R R R R R R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit symbol name Description 15 to 2 Reserved bit...

Page 262: ...perature variation the software performs the frequency adjustment according to the temperature by using the frequency adjustment function in the low speed RC oscillation circuit The software calculate...

Page 263: ...ns a program after 10 counts of the low speed RC oscillation clock The frequency of the low speed RC oscillation circuit can be adjusted with the low speed RC oscillation frequency adjustment register...

Page 264: ...RC Oscillation Circuit and in STOP STOP D Mode RC oscillation waveform STOP mode LSCLK supply started CPU operation start Power supply VDD Power on reset LSCLK supply started External interrupt occurr...

Page 265: ...mode The state on the LSI transfers to the backup mode in the following three cases The low speed crystal oscillation circuit is chosen for the low speed clock through the FLMOD register The STOP STOP...

Page 266: ...n clock is supplied to the low speed clock LSCLK In addition the low speed crystal oscillation circuit stops oscillation when entering the STOP STOP D mode It resumes the oscillation by releasing the...

Page 267: ...CBUINT occurs when the crystal oscillation stops and when the crystal oscillation resumes Figure 6 7 Low speed Crystal Oscillation Circuit Operation Backup Mode Low speed RC oscillation Clock backup i...

Page 268: ...ailable on the ML62Q1300 group A low speed external clock can be chosen in the low speed clock mode register FLMOD When choosing the low speed external clock for a low speed clock the XT1 pin forcibly...

Page 269: ...tting the stabilized frequency the clock supply is started approximately 30 s after the high speed clock oscillation is enabled The clock frequency reaches to the target approximately 2 ms after the h...

Page 270: ...shows WDT clock operation waveforms at the start of the WDT RC oscillation circuit and in the STOP STOP D mode Figure 6 11 WDT RC Oscillation Circuit Configuration Figure 6 12 Operation Waveforms at S...

Page 271: ...aiting for the high speed oscillation stabilization time Set the frequency dividing ratio of the high speed clock 1 1 to 1 32 HSCLK can be chosen Setting of FCON Writing of FHCKMOD Writing of FHWUPT V...

Page 272: ...coming incapable of processing interrupts in time If interrupts frequently occur for reasons such as short interrupt cycles of peripheral circuits take into account the operating frequency of the CPU...

Page 273: ...the low speed external clock 2 Do not control the power managements write to SBYCON register and the clock managements write to LOSCM 1 0 of FLMOD register and write to SELSCLK of FCON register before...

Page 274: ...Chapter 7 Low Speed Time Base Counter...

Page 275: ...Speed Time Base Counter 7 1 General Description The low speed time base counter enables following functions Generate periodical interrupt requests Output periodical pulse signals to the general ports...

Page 276: ...t LTBC0INT can be used for a trigger event source of the Successive Approximation type A D Converter ML62Q1500 and ML62Q1700 group The clock frequency adjust function Allows to adjust in a range appro...

Page 277: ...r ML62Q1300 group T1HZ to T128HZ Time base counter output signal LTBC2INT Low speed time base counter 2 interrupt request LTBC1INT Low speed time base counter 1 interrupt request LTBC0INT Low speed ti...

Page 278: ...request LTBC0INT Low speed time base counter 0 interrupt request T2HZR Simplified RTC 2Hz Clock T1HZR Simplified RTC 1Hz Clock Figure 7 2 Configuration of Low Speed Time Base Counter ML62Q1500 and ML6...

Page 279: ...rt and the register setting Pin name Shared port Setting register Setting value ML62Q1300 group ML62Q1500 ML62Q1700 group 16pin product 20 pin product 24 pin product 32 pin product 48 pin product 52 p...

Page 280: ...0 0xF061 Reserved R 8 0x00 0xF062 Low speed Time Base Counter Control register LTBCCON R W 8 0x01 0xF063 Reserved R 8 0x00 0xF064 Simplified RTC Time Base Counter register LTBRR R W 8 0x00 0xF065 Rese...

Page 281: ...y occur depending on a write timing to the LTBR See the program example for initializing described in Section 7 3 1 Operation of the Low speed Time Base Counter T128HZ to T1HZ signals have 0 level in...

Page 282: ...2Q1700 group 0 General frequency adjustment mode Initial value 1 Virtual frequency adjustment mode 6 LTCO This bit is used to choose the signal that is output from TBCOUT0 pin and TBCOUT1 pin 0 T1HZ I...

Page 283: ...ess 0xF064 LTBRR Access R W Access size 8 bit Initial value 0x00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word Byte LTBRR Bit T1HZ R T2HZ R T4HZ R T8HZ R T16H ZR T32H ZR T64H ZR T128 HZR R W R R R R R R...

Page 284: ...8 7 6 5 4 3 2 1 0 Word LTBADJ Byte LTBADJH LTBADJL Bit LADJ S LADJ 11 LADJ 10 LADJ 9 LADJ 8 LADJ 7 LADJ 6 LADJ 5 LADJ 4 LADJ 3 LADJ 2 LADJ 1 LADJ 0 R W R R R R W R W R W R W R W R W R W R W R W R W R...

Page 285: ...W R W R W R R W R W R W Initial value 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 0 Bit No Bit symbol name Description 15 to 11 Reserved bit 10 to 8 LTI2S2 to LTI2S0 These bits are used to choose the signal to be...

Page 286: ...Speed Time Base Counter FEUL62Q1000 7 12 Note A time base counter interrupt may occur depending on a write timing to the LTBINTL or LTLBINTH See the program example for initializing described in 7 3 1...

Page 287: ...speed time base counter interrupt request bit QLTBCn bit of IRQ67 register n 0 to 2 to become 1 after changing the LTBINT register Therefore place one NOP instruction after changing the LTBINT regist...

Page 288: ...by Writing to LTBR Register Note After writing to the LTBR register the time by which the first low speed time base counter interrupt request is generated is not guaranteed If measuring the time using...

Page 289: ...cycle of 0 5 seconds using HSCLK T2HZ T1HZ T2HZR and T1HZR outputs can be adjusted Table 7 2 Frequency adjustment value set in the LTBADJ and Adjustment ratio LADJS LADJ11 to 0 Hexadecimal Frequency a...

Page 290: ...ation of the low speed oscillation 32 768 kHz due to temperature variations 7 3 3 The way of monitoring the frequency on LCD drive outputs The adjusted frequency by the LTBADJ register can be confirme...

Page 291: ...Chapter 8 16 Bit Timer...

Page 292: ...cy to the general ports Output one shot pulse signals to the general ports Count up the rising edges of the external input signal The number of 16 bit timer channels is dependent of the product specif...

Page 293: ...d operation until stop by the software One shot mode Count able to the max 0xff Run the specified operation once and stop it One channel of 16 bit timer is configurable as two channels of 8 bit timer...

Page 294: ...egister Compare TMHnCH TMHnCL 8 bit counter Timer control TMHnMD TMHSTR TMHSTP TMHSTAT Interrupt control TMHnIS TMHnIC Port output control TMHnOUT TMnINT Compare Data register 8 bit counter EXTRG0 EXT...

Page 295: ...duct 48 pin product 52 pin product 64 pin product 80 pin product 100 pin product EXI0 P02 Primary Func P0MOD2 0000_0X01 1 EXI1 P03 P0MOD3 0000_0X01 1 TMH0OUT P04 5 th Func P0MOD4 0100_XXXX 2 TMH1OUT P...

Page 296: ...timer 1counter register TMH1CL TMH1C R W 8 16 0x00 0xF313 TMH1CH R W 8 0x00 0xF314 16 bit timer 2 counter register TMH2CL TMH2C R W 8 16 0x00 0xF315 TMH2CH R W 8 0x00 0xF316 16 bit timer 3 counter reg...

Page 297: ...er 7 interrupt status register TMH7ISL TMH7IS R 8 16 0x00 0xF33F TMH7ISH R 8 0x00 0xF340 16 bit timer 0 interrupt clear register TMH0ICL TMH0IC W 8 16 0x00 0xF341 TMH0ICH W 8 0x00 0xF342 16 bit timer...

Page 298: ...9 TMH4DH 0xF30A TMH5DL TMH5D 0xF30B TMH5DH 0xF30C TMH6DL TMH6D 0xF30D TMH6DH 0xF30E TMH7DL TMH7D 0xF30F TMH7DH Access R W Access size 8 16 bit Initial value 0xFFFF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 299: ...reset to 0x00 When the value of TMHnDL register coincides with that of the TMHnCL register the TMHnCL is reset to 0x00 Also when the value of TMHnDH register coincides with that of the TMHnCH registe...

Page 300: ...0 Positive logic initial level is L initial value 1 Negative logic initial level is H 9 THnOST This bit is used to choose the operation mode of the 16 bit timer n 0 Repeat timer mode initial value 1 O...

Page 301: ...lue 1 HSCLK Note Input the pulse for the external trigger with the width of two timer clocks or longer Set TMHnMOD when the timer n is stopped THnSTAT THnHSTAT bits of TMHSTAT register are 0 If it is...

Page 302: ...xF333 TMH1ISH 0xF334 TMH2ISL TMH2IS 0xF335 TMH2ISH 0xF336 TMH3ISL TMH3IS 0xF337 TMH3ISH 0xF338 TMH4ISL TMH4IS 0xF339 TMH4ISH 0xF33A TMH5ISL TMH5IS 0xF33B TMH5ISH 0xF33C TMH6ISL TMH6IS 0xF33D TMH6ISH 0...

Page 303: ...48 TMH4ICL TMH4IC 0xF349 TMH4ICH 0xF34A TMH5ICL TMH5IC 0xF34B TMH5ICH 0xF34C TMH6ICL TMH6IC 0xF34D TMH6ICH 0xF34E TMH7ICL TMH7IC 0xF34F TMH7ICH Access W Access size 8 16 bit Initial value 0x0000 15 14...

Page 304: ...name Description 15 TH7HRUN In the 8bit timer mode controls the upper side 8bit counter of 16bit timer 7 Writing 0 Invalid Writing 1 Start counting 14 TH6HRUN In the 8bit timer mode controls the upper...

Page 305: ...r 4 Writing 0 Invalid Writing 1 Start counting 3 TH3RUN In the 16bit timer mode controls the counter of 16bit timer 3 In the 8bit timer mode controls the lower side 8bit counter of 16bit timer 3 Writi...

Page 306: ...ol name Description 15 TH7HSTP In the 8bit timer mode controls the upper side 8bit counter of 16bit timer 7 Writing 0 Invalid Writing 1 Stop counting 14 TH6HSTP In the 8bit timer mode controls the upp...

Page 307: ...r 4 Writing 0 Invalid Writing 1 Stop counting 3 TH3STP In the 16bit timer mode controls the counter of 16bit timer 3 In the 8bit timer mode controls the lower side 8bit counter of 16bit timer 3 Writin...

Page 308: ...ing is in progress 14 TH6HSTAT In the 8bit timer mode indicates the status on the upper side 8bit counter of 16bit timer 6 0 The counting is stopped Initial value 1 The counting is in progress 13 TH5H...

Page 309: ...it timer mode indicates the status on the lower side 8bit counter of 16bit timer 4 0 The counting is stopped Initial value 1 The counting is in progress 3 TH3STAT In the 16bit timer mode indicates the...

Page 310: ...bit of the HnMOD register In the 16 bit timer mode following two operation modes are available Repeat mode One shot mode 8 3 1 1 Repeat Mode Figure 8 3 shows the repeat mode operation in the 16 bit ti...

Page 311: ...value TMI Initial value Figure 8 4 One shot Mode Operation Timing in 16 Bit Timer Mode In the one shot mode when the timer count value matches with the TMHnD register 16 bit timer n interrupt TMnINT...

Page 312: ...bit timer mode Stop timer Repeat mode or One shot mode operation Set a comparison value into TMHnD register that is to be compared with TMHnC register QTMn 0 Reset corresponding bits of IRQ45 register...

Page 313: ...wing two operation modes are available Repeat mode One shot mode 8 3 2 1 Repeat Mode Figure 8 6 shows the repeat mode operation in the 8 bit timer mode TMHnDL setting value THnHSTAT TMHn Interrupt TMH...

Page 314: ...nDH register setting value 0x01 to 0xFF THnCK Count clock frequency chosen in the TMHnMOD register TTMIL TMHnDL 1 n 0 to 7 THnCK Hz TMHnDL TMHnDL register setting value 0x01 to 0xFF THnCK Count clock...

Page 315: ...atch Initial value Figure 8 7 One shot Mode Operation Timing in 8 Bit Timer Mode In the one shot mode if the upper side 8 bit timer count value matches with the TMHnDH register value the timer count v...

Page 316: ...at is to be compared with TMHnC register QTMn 0 Reset corresponding bits of IRQ45 register and IRQ67 register to 0 ETMn 1 Set corresponding bits of IE45 register and IE67 register to 1 TMHnC 0x0000 Wr...

Page 317: ...er value 0 0 Generated 0 1 Not generated 1 0 1 1 Lower side 8 bit timer count value matches TMHnDL register value 0 0 Generated 0 1 Not generated 1 0 1 1 If an 8 bit timer interrupt of the other side...

Page 318: ...lock is LSCLK and frequency dividing ratio of the count clock is 1 2 of the timer clock SYSTEMCLK FFF0H Timer clock Timer counter THnSTAT Timer stop TMHnOUT FFF1H Write TMHSTP register FFF2H Figure 8...

Page 319: ...s input mode Choose an external input pin When using EXTRG0 P02IE 1 When using EXTRG1 P03IE 1 Set the external input for the count clock When using EXTRG0 THnEXS 0 When using EXTRG1 THnEXS 1 THnEX 1 C...

Page 320: ...Chapter 9 Functional Timer FTM...

Page 321: ...e the MCU generates two types of PWM waveform that have the same cycle and the start timing The setting value of FTnEA register makes the duty of FTMnP pin output signal and the setting value of FTnEB...

Page 322: ...f the product specification Table 9 1 shows the number of channels Table 9 1 Number of Functional Timer channels Channel no ML62Q1300 group ML62Q1500 ML62Q1700 group 16pin product 20pin product 24pin...

Page 323: ...a duty interrupt and a coincident interrupt with the setting value as well as a cyclic interrupt One shot mode is available Start stop clear the timer by an external trigger input or a timer interrup...

Page 324: ...ternal clock CMP0D Comparator 0 TMH0TRG to TMH5TRG 16 bit Timer n trigger n 0 to 3 Figure 9 1 Configuration of the Functional Timer CMP0D Analog comparator TMH0TRG toTMH5TRG 16bit timer EXTRG0 to EXTR...

Page 325: ...List of Pins The I O pins of the Functional timer are assigned to the shared function of the general ports Pin name I O Description EXTRG0 to EXTRG7 I External trigger n External clock n FTMnPn O Fun...

Page 326: ...P20 5 th Func P2MOD0 0100_XXXX 2 P46 5 th Func P4MOD6 0100_XXXX 2 1 1 1 2 FTM2P P21 5 th Func P2MOD1 0100_XXXX 2 FTM2N P22 5 th Func P2MOD2 0100_XXXX 2 3 FTM3P P01 5 th Func P0MOD1 0100_XXXX 2 1 1 1...

Page 327: ...T0EAL FT0EA R W 8 16 0x00 0xF411 FT0EAH R W 8 0x00 0xF412 FTM1 event A register FT1EAL FT1EA R W 8 16 0x00 0xF413 FT1EAH R W 8 0x00 0xF414 FTM2 event A register FT2EAL FT2EA R W 8 16 0x00 0xF415 FT2EA...

Page 328: ...43C FTM6 dead time register FT6DTL FT6DT R W 8 16 0x00 0xF43D FT6DTH R W 8 0x00 0xF43E FTM7 dead time register FT7DTL FT7DT R W 8 16 0x00 0xF43F FT7DTH R W 8 0x00 0xF440 FTM0 counter register FT0CL FT...

Page 329: ...W 8 0x40 0xF46C FTM6 mode register FT6MODL FT6MOD R W 8 16 0x00 0xF46D FT6MODH R W 8 0x40 0xF46E FTM7 mode register FT7MODL FT7MOD R W 8 16 0x00 0xF46F FT7MODH R W 8 0x40 0xF470 FTM0 clock register F...

Page 330: ...0 0xF49A FTM5 trigger register 1 FT5TRG1L FT5TRG1 R W 8 16 0x00 0xF49B FT5TRG1H R W 8 0x00 0xF49C FTM6 trigger register 1 FT6TRG1L FT6TRG1 R W 8 16 0x00 0xF49D FT6TRG1H R W 8 0x00 0xF49E FTM7 trigger...

Page 331: ...00 0xF4C4 FTM2 interrupt clear register FT2INTCL FT2INTC W 8 16 0x00 0xF4C5 FT2INTCH W 8 0x00 0xF4C6 FTM3 interrupt clear register FT3INTCL FT3INTC W 8 16 0x00 0xF4C7 FT3INTCH W 8 0x00 0xF4C8 FTM4 int...

Page 332: ...T4P 0xF409 FT4PH 0xF40A FT5PL FT5P 0xF40B FT5PH 0xF40C FT6PL FT6P 0xF40D FT6PH 0xF40E FT7PL FT7P 0xF40F FT7PH Access R W Access size 8 16 bit Initial value 0xFFFF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Page 333: ...8 FTnE A7 FTnE A6 FTnE A5 FTnE A4 FTnE A3 FTnE A2 FTnE A1 FTnE A0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit no Bit symbol na...

Page 334: ...15 FTnE B14 FTnE B13 FTnE B12 FTnE B11 FTnE B10 FTnE B9 FTnE B8 FTnE B7 FTnE B6 FTnE B5 FTnE B4 FTnE B3 FTnE B2 FTnE B1 FTnE B0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Init...

Page 335: ...6DTH 0xF43E FT7DTL FT7DT 0xF43F FT7DTH Access R W Access size 8 16 bit Initial value 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word FTnDT Byte FTnDTH FTnDTL Bit FTnD T15 FTnD T14 FTnD T13 FTnD T12...

Page 336: ...xF443 FT1CH 0xF444 FT2CL FT2C 0xF445 FT2CH 0xF446 FT3CL FT3C 0xF447 FT3CH 0xF448 FT4CL FT4C 0xF449 FT4CH 0xF44A FT5CL FT5C 0xF44B FT5CH 0xF44C FT6CL FT6C 0xF44D FT6CH 0xF44E FT7CL FT7C 0xF44F FT7CH Ac...

Page 337: ...by reading FTnC register in one clock of the timer clock 0 Start by the event trigger is enabled initial value 1 Start by the event trigger is disabled 5 FTnFLGB This bit is used to indicate the state...

Page 338: ...the phase of signal output at FTMnN pin and FTMnP pin FTMnN pin output FTMnP pin output 00 Output Negative phase Output Negative phase 01 Output Negative phase initial value Output Positive phase ini...

Page 339: ...nto the FTnEA or FTnEB register the next capture is not performed until reading the data When the counter goes round it stops 6 rsvd Reserved bit 5 FTnDTENN This bit is used to enable the dead time of...

Page 340: ...0 0 0 0 0 0 0 0 0 0 0 0 0 Bit no Bit symbol name Description 15 to 11 Reserved bit 10 to 8 FTnXCK2 to FTnXCK0 These bits are used to choose the external clock input used when the FTnEX bit is 1 000 E...

Page 341: ...l name Description 2 1 Reserved bit 0 FTnCK0 This bit is used to choose the timer clock FTnTCK in the FTMn 0 LSCLK Initial value 1 HSCLK Note The pulse input to the EXTRG0 to EXTRG7 pin must have the...

Page 342: ...FT7TRG0 0xF48F FT7TRG0H Access R W Access size 8 16 bit Initial value 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word FTnTRG0 Byte FTnTRG0H FTnTRG0L Bit FTnE ST1 FTnE ST0 FTnS TSS FTnS TS3 FTnS TS2...

Page 343: ...r 3 Trigger TMH3TRG 10100 16 bit Timer 4 Trigger TMH4TRG 10101 16 bit Timer 5 Trigger TMH5TRG 10110 16 bit Timer 6 Trigger TMH6TRG 10111 16 bit Timer 7 Trigger TMH7TRG 11000 Functional Timer 0 Trigger...

Page 344: ...t 0 The counter stop is disabled Initial value 1 The counter stop is enabled 1 FT STC This bit is used to choose whether to enable clearing the counter when a trigger event for counter start occurs on...

Page 345: ...d to set the noise removal width of the external trigger EXTRG0 to EXTRG7 and CMP0D It can make a delay time by the noise filter or trigger before starting the trigger These bits are valid to use when...

Page 346: ...Note When using the COMP0D EXTRG0 and EXTRG4 as the emergency stop trigger the noise filter function set by the FTnTRF2 to 0 bits of FTnTRG1 register are invalid Use another filter function in each pe...

Page 347: ...nIOB This bit is used to enable FTMnTRG output in event timing B of FTMn When it s enabled the FTMnTRG is output when the data of FTnC register and FTnEB register matched or a data is captured into th...

Page 348: ...ite always 0 1 Do not set CAPTURE mode 0 Capture B interrupt is disabled 1 Capture B interrupt is enabled 1 FTnIEA This bit is used to enable the event timing A interrupt in TIMER PWM1 and PWM2 mode o...

Page 349: ...nterrupt has not occurred initial value 1 Emergency stop interrupt has occurred This bit is cleared when writing 1 to FTnICES bit of FTnINTC register 4 FTnISTR This bit is used to indicate the state o...

Page 350: ...t occurred initial value 1 Event timing A interrupt has occurred This bit is cleared by writing 1 to FTnICA bit of FTnINTC register CAPTURE mode 0 Capture A interrupt has not occurred 1 Capture A inte...

Page 351: ...W W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit no Bit symbol name Description 15 FTnIR An interrupt request bit of FTMn Writing 0 Invalid Writing 1 If there is any unhandled interrupt source t...

Page 352: ...FTCU D6 FTCU D5 FTCU D4 FTCU D3 FTCU D2 FTCU D1 FTCU D0 R W R R R R R R R R W W W W W W W W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit no Bit symbol name Description 7 to 0 FTCUD7 to FTCUD0 Th...

Page 353: ...T3E MGEN FT3E MGEN FT3E MGEN FT2E MGEN FT1E MGEN FT0E MGEN R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit no Bit symbol name Desc...

Page 354: ...it no Bit symbol name Description 15 to 8 FT7ETG to FT0ETG These bits are used to enable counting stop start by a trigger event Control by the FTCSTP register to disable it For clearing the counter by...

Page 355: ...no Bit symbol name Description 15 to 8 FT7DTG to FT0DTG These bits are used to disable counting stop start by a trigger event Control by the FTCSTR register to enable it Trigger operation is enabled...

Page 356: ...GEN FT7R UN FT6R UN FT5R UN FT4R UN FT3R UN FT2R UN FT1R UN FT0R UN R W R R R R R R R R R R R R R R R R Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit no Bit symbol name Description 15 to 8 FT7TGE...

Page 357: ...gger setting FTnTRG0 register FTnTRG1 register Use this setting when starting stopping the counter by an event trigger In the FTnTRG0 register choose the event trigger source and the action In the FTn...

Page 358: ...A bit becomes 1 at the start after one cycle of the count clock After two cycles the counter operation starts When the operation is stopped the count operation stops after one cycle of the count clock...

Page 359: ...s 0 When writing 1 to the FTnSTP bit of the FTCSTP register while the counter operation is in progress the FTnSTA bit of the FTnSTAT register showing the count status is 1 the counter stops its operat...

Page 360: ...t set in the FTnDT register elapses In the repeat mode the output repeats to toggle the signal level synchronizing with the start of count and the overflow In the one shot mode the positive output rem...

Page 361: ...put phase to the FTMnP FTMnN pins specified by the FTnOSL1 and FTnOSL0 bits of the FTnMOD register Figure 9 4 b shows waveforms when reversing the output to the FTMnP pin by the FTnOSNP bit and revers...

Page 362: ...nOSNN 0 FTnOSNP 0 Positive phase No reverse Negative phase No reverse Positive phase Reverse FTnOSNN 0 FTnOSNP 1 FTMnN Negative phase No reverse FTnOSNN 1 FTnOSNP 0 FTMnP Positive phase No reverse FTM...

Page 363: ...5 Output waveforms in TIMER mode When counter stop FTnP Counter FTnSTA a FTnSTPO 0 1 2 3 4 2 5 1 4 2 3 4 2 4 5 1 Positive phase Counter operation 1 Counter operation start 2 Counter operation stop 3 C...

Page 364: ...TnTRG0 register 0000 to FTnSTS3 to FTnSTS0 bits to set the source of the trigger event to EXTRG0 Write 1 to the FTnST bit to enable the start function of the counter Write 1 to the FTnSP bit to enable...

Page 365: ...Operation Example to measure cycle and duty of PWM signal repeat cycle 1 The counter starts operating at the rising edge of the signal input from the P02 EXTRG0 pin 2 The value of the counter registe...

Page 366: ...is restarted with the the signal rising again a When read the register before the next trigger common to FTnOST 0 1 b When not read the register before the next trigger FTnOST 0 c When not read the re...

Page 367: ...n repeats until the operation is stopped In the one shot mode they automatically stops after one cycle becoming L level In addition if the dead time is enabled the L level output is maintained from th...

Page 368: ...ase to the FTMnP FTMnN pins specified by the FTnOSL1 and FTnOSL0 bits of the FTnMOD register Figure 9 10 b shows waveforms when reversing the output to the FTMnP pin by the FTnOSNP bit and reversing t...

Page 369: ...NN 0 FTnOSNP 0 FTMnP FTMnN FTnOSNN 0 FTnOSNP 1 Positive phase No reverse Negative phase No reverse FTMnP FTMnN FTnOSNN 1 FTnOSNP 0 FTMnP FTMnN FTnOSNN 1 FTnOSNP 1 FTMnP FTMnN b Output reverse specifie...

Page 370: ...WM1 Mode Output Waveform when counter stop FTnP Positive phase Negative phase a FTnSTPO 0 FTnEA FTnEB FTnSTR 4 2 3 4 2 5 Counter operation 1 Counter operation start 2 Counter operation stop 3 Counter...

Page 371: ...his pattern repeats until the operation is stopped In the one shot mode they automatically stops after one cycle becoming L level In addition if the dead time is enabled the L level output is maintain...

Page 372: ...tput phase to the FTMnP FTMnN pins specified by the FTnOSL1 and FTnOSL0 bits of the FTnMOD register Figure 9 13 b shows waveforms when reversing the output to the FTMnP pin by the FTnOSNP bit and reve...

Page 373: ...0 FTnOSNP 0 FTMnP FTMnN FTnOSNN 0 FTnOSNP 1 Positive phase No reverse Negative phase No reverse FTMnP FTMnN FTnOSNN 1 FTnOSNP 0 FTMnP FTMnN FTnOSNN 1 FTnOSNP 1 FTMnP FTMnN b Output reverse specified b...

Page 374: ...9 14 PWM2 Mode Output Waveform when counter stop FTnP Positive phase Negative phase a FTnSTPO 0 FTnEA FTnSTR Counter operation 1 Counter operation start 2 Counter operation stop 3 Counter operation re...

Page 375: ...e chosen using the port controller register In addition the sampling controller is installed also in the functional timer It can be set through FTnTRF2 to FTnTRF0 bits of the FTnTRG1 register If EXTRG...

Page 376: ...anging the setting choose the timer clock again Once the configuration above is completed control the counter by the FTCSTR register The procedure is as follows 1 Make the waiting state for an event t...

Page 377: ...ISES bit of the FTnINTS register becomes 1 see 2 in Figure 9 17 When the FTnISES bit is 1 even if the event trigger of counter start is generated it is not accepted If the event trigger for the counte...

Page 378: ...If the counter is restarted in this state the Positive Negative phase output remains at L level during the present period and changes according to the count value from the next period 2 If the FTnSTPO...

Page 379: ...is set to 1 Figure 9 18 shows the operating waveforms when the registers are updated while the counter stops counter value is 0x0000 or the counter is operating Figure 9 19 shows the operating wavefor...

Page 380: ...counter value is other than 0x0000 3 The counter operation restarts Each buffer is not updated at this timing 4 Set FTCUDn bit to 1 5 Each buffer is updated at the start of cycle and the FTCUDn bit g...

Page 381: ...iod coincident interrupt All modes FTnISP bit Write 1 to FTnICP bit Event A coincident interrupt TIMER PWM1 PWM2 FTnISA bit Write 1 to FTnICA bit Capture A interrupt CAPTURE FTnISA bit Write 1 to FTnI...

Page 382: ...Chapter 10 Watchdog Timer...

Page 383: ...s generated in the first overflow if the window function is enabled If the counter is cleared in the unexpected time period the WDT invalid clear reset is generated if the window function is enabled T...

Page 384: ...d mode WDT interrupt WDT reset Window function enabled mode WDT reset Generation enabled The following items can be chosen by the code option See the Chapter 26 Code Option for details of the code opt...

Page 385: ...chdog timer counter register WDTSTA Watchdog timer status register Figure 10 2 Configuration of Watchdog Timer Data bus WDT counter WDT overflow reset WDT interrupt WDTINT interrupt WDT overflow WDTMO...

Page 386: ...value byte Word 0xF010 Watchdog timer control register WDTCON R W 8 0x00 0xF011 Reserved register R 8 0x00 0xF012 Watchdog timer mode register WDTMOD R W 8 0x06 0xF013 Reserved register R 8 0x00 0xF0...

Page 387: ...7 to 0 d7 to d0 The WDT counter can be cleared by writing 0x5A with the WDP bit set to 0 then writing 0xA5 with the WDP bit set to 1 In the window mode WDT invalid clear reset is generated if the WDT...

Page 388: ...de 2 the clear enabled period is approximately 50 of the overflow period 11 Setting disabled setting of window function enabled mode 2 If the overflow period of the WDT counter is set to 62 5 ms or le...

Page 389: ...8 WDTC 7 WDTC 6 WDTC 5 WDTC 4 WDTC 3 WDTC 2 WDTC 1 WDTC 0 R W R R R R R R R R R R R R R R R R Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit name Description 15 to 0 WDTC15 to WDTC0 These bi...

Page 390: ...is completed See Figure 10 3 for details of operation waveforms of the WDTCLR2 bit 0 No WDT counter clearing initial value 1 WDT counter clearing in progress 1 WDTCLR1 This bit is used to read the sta...

Page 391: ...WDT interrupt is generated when the counter overflows for the first time and the WDT reset is generated when the counter overflows a second time Window function enabled mode The periods during which W...

Page 392: ...ter Clearing Timing Chart The following description shows a sample program script of the watchdog timer void wdt_clear void unsigned char pswval if WDTCLR1 1 Checking presence of pending clearing proc...

Page 393: ...ister and clearing of the WDT counter To enter the STOP mode or STOP D mode following WDT clearing do so after making sure that the WDTCLR1 bit became 0 In addition if changing the WDTMOD register set...

Page 394: ...curs and the state on the LSI is transferred to the system reset mode See Chapter 3 Reset Function for details of the RSTAT register Figure 10 5 Procedure to Use WDT in Window Function Disabled Mode S...

Page 395: ...1 2 0 0 0 7 8 ms 15 6 ms Overflow period 0 0 1 15 6 ms 31 3 ms Overflow period 0 1 0 31 3 ms 62 5 ms Overflow period 0 1 1 62 5 ms 125 ms Overflow period 1 0 0 125 ms 250 ms Overflow period 1 0 1 500...

Page 396: ...erflow Period 8000 ms WDT counter value 0 Time Overflow period TWOV 7998 ms WDT interrupt generated WDT reset generated WDT cleared enabled The clear processing is enable for two clocks of the WDTCLK...

Page 397: ...use the internal pointer WDP is 1 Internal pointer WDP 1 0 7 Although 0xA5 is written to the WDTCON register the WDT counter is not cleared because the internal pointer WDP is 0 and writing of 0x5A is...

Page 398: ...of modes can be chosen through the WDTMOD register Window function enabled mode 1 the clear enabled period is approximately 75 of the overflow period Window function enabled mode 2 the clear enabled p...

Page 399: ...e 1 Operation Overview Figure 10 11 Window Function Enabled Mode 2 Operation Overview 75 WDT counter value 0 Time 75 for clear enabled period TWCL WDT counter clear Overflow period TWOV 25 for clear d...

Page 400: ...r Enabled Period in Window Function Enabled Mode 2 WDT2 WDT1 WDT0 Overflow period TWOV 1 WDT reset generation time 1 WDT clear enabled period TWCL 1 2 0 0 0 Approx 7 8 ms Approx 7 8 ms Overflow period...

Page 401: ...rnal pointer WDP 1 0 5 0x5AH is written to WDTCON during the WDT clear enabled period Internal pointer WDP 0 1 6 Occurrence of abnormality 7 The WDT counter overflows and a WDT reset occurs Internal p...

Page 402: ...Chapter 11 Serial Communication Unit...

Page 403: ...rial interface UART Universal Asynchronous Receiver Transmitter The number of serial communication unit channels is dependent of the product specification Table 11 1 shows the number of channels Table...

Page 404: ...Function 16 bit mode UART mode Half duplex communication 5 bit 6 bit 7 bit 8 bit data length Odd parity even parity 0 parity 1 parity and no parity One stop bit Two stop bits Positive logic negative l...

Page 405: ...SIOnSTAT SSIOn status register UAnMOD UARTn mode register UAnBRT UARTn baud rate register UAnSTAT UARTn status register SIUn0INT Serial communication unit n0 Interrupt SIUn1INT Serial communication un...

Page 406: ...7 GPIO n 0 to 5 Pin name I O Description SUn_RXD0 I UART0 data input of serial communication unit n SUn_RXD1 I UART1 data input of serial communication unit n SUn_TXD0 O UART0 data output of serial co...

Page 407: ...3 rd Func P1MOD3 0010_XXXX 1 P20 2 nd Func P2MOD0 0001_XXXX 1 SU0_RXD1 P07 2 nd Func P0MOD7 0001_XXXX 2 P17 2 nd Func P1MOD7 0001_XXXX 2 1 SU1_TXD0 P22 2 nd Func P2MOD2 0001_XXXX 1 P25 2 nd Func P2MOD...

Page 408: ...1 SU4_RXD1 P44 2 nd Func P4MOD4 0001_XXXX 2 P52 2 nd Func P5MOD2 0001_XXXX 2 5 SU5_TXD0 P84 2 nd Func P8MOD4 0001_XXXX 1 1 PB3 2 nd Func PBMOD3 0001_XXXX 1 SU5_RXD0 P83 2 nd Func P8MOD3 0001_XXXX 2 1...

Page 409: ...2 0001_XXXX 1 P25 2 nd Func P2MOD5 0001_XXXX 1 2 SU2_SIN P56 2 nd Func P5MOD6 0001_XXXX 2 SU2_SCLK PA3 2 nd Func PAMOD3 0001_XXXX 3 SU2_SOUT P57 2 nd Func P5MOD7 0001_XXXX 1 3 SU3_SIN P64 2 nd Func P6...

Page 410: ...K P23 SU1_SCLK PA3 SU2_SCLK P66 SU3_SCLK Input output pin Combination 9 Combination 10 Combination 11 SUn_SIN P80 SU4_SIN P93 SU4_SIN PB2 SU5_SIN SUn_SOUT P81 SU4_SOUT P94 SU4_SOUT PB3 SU5_SOUT SUn_SC...

Page 411: ...ort 0 mode register SIO0MODL SIO0MOD R W 8 16 0x00 0xF609 SIO0MODH R W 8 0x00 0xF60A Synchronous serial port 0 status register SIO0STAT R W 8 0x00 0xF60B Reserved R 8 0x00 0xF60C UART00 mode register...

Page 412: ...MODL SIO1MOD R W 8 16 0x00 0xF629 SIO1MODH R W 8 0x00 0xF62A Synchronous serial port 1 status register SIO1STAT R W 8 0x00 0xF62B Reserved R 8 0x00 0xF62C UART10 mode register UA10MODL UA10MOD R W 8 1...

Page 413: ...MODL SIO2MOD R W 8 16 0x00 0xF649 SIO2MODH R W 8 0x00 0xF64A Synchronous serial port 2 status register SIO2STAT R W 8 0x00 0xF64B Reserved R 8 0x00 0xF64C UART20 mode register UA20MODL UA20MOD R W 8 1...

Page 414: ...MODL SIO3MOD R W 8 16 0x00 0xF669 SIO3MODH R W 8 0x00 0xF66A Synchronous serial port 3 status register SIO3STAT R W 8 0x00 0xF66B Reserved R 8 0x00 0xF66C UART30 mode register UA30MODL UA30MOD R W 8 1...

Page 415: ...O4MODL SIO4MOD R W 8 16 0x00 0xF689 SIO4MODH R W 8 0x00 0xF68A Synchronous serial port 4 status register SIO4STAT R W 8 0x00 0xF68B Reserved R 8 0x00 0xF68C UART40 mode register UA40MODL UA40MOD R W 8...

Page 416: ...MODL SIO5MOD R W 8 16 0x00 0xF6A9 SIO5MODH R W 8 0x00 0xF6AA Synchronous serial port 5 status register SIO5STAT R W 8 0x00 0xF6AB Reserved R 8 0x00 0xF6AC UART50 mode register UA50MODL UA50MOD R W 8 1...

Page 417: ...Transmission Interval Setting Register SUnDLYL Transmit only Serial Communication Unit n Control Register SUnCONL Use SnEN only Use Un0EN only Use Un0EN only SUnCONH Use Un1EN only Synchronous Serial...

Page 418: ...ive data buffer for the upper side 8bit If writing data into this register the data is stored into the transmission register SUnTR If reading data the data in the reception data SUnRC is read out UART...

Page 419: ...SDnBUFH register after checking Un1FUL bit of UARTn1 status register UAn1STAT is 0 The written data in the SDnBUFH register can be read out When choosing the 5 to 7 bit length written data in unused b...

Page 420: ...nterrupt occurs at the end of data transmission Initial 1 The Interrupt occurs at the start and end of data transmission When the SUnINTS bit is 1 0 The interrupt occurs at the end of data transmissio...

Page 421: ...W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit no Bit symbol name Description 7 to 0 SUnDLY7 to SUnDLY0 These bits are used to set the transmission frame interval in the SSIO mode or UART mode Wh...

Page 422: ...lock SUnMD1 SUnMD0 SnCK4 SnCK3 SnCK2 SnCK1 0 0 1 0 0 0 0 LSCLK Initial value 1 0 0 1 0 1 HSCLK UART mode SUnMOD UAnMOD Base clock SUnMD1 SUnMD0 UnCK1 1 0 0 LSCLK 1 HSCLK 1 1 0 LSCLK 1 HSCLK Note Set 0...

Page 423: ...Bit no Bit symbol name Description 15 to 10 Reserved bit 9 Un1EN This bit is used to enable the UARTn1 communication in the half duplex mode UART Half duplex mode 0 Stop the UARTn1 communication Initi...

Page 424: ...Bit symbol name Description 15 Reserved bit 14 SnNEG This bit is used to choose logic of the transfer clock in the SSIO mode 0 Positive logic initial value 1 Negative logic 13 SnCKT This bit is used t...

Page 425: ...ode 10 Transmit mode 11 Transmit Receive mode 0 SnDIR This bit is used to choose the communication direction in the SSIO mode 0 LSB first Initial value 1 MSB first Note Be sure to set the SIO0MOD regi...

Page 426: ...bit is used to indicate transmitting data in the SSIO mode 0 Data transmission is stopped Initial value 1 Data transmission is in progress 3 SnFUL This bit is used to indicate state of the transmissi...

Page 427: ...the SnTUER bit write 1 to this bit The SnTUER bit is fixed to 0 in the reception mode 0 There was no transmission underrun error Initial value 1 There was a transmission underrun error Note Do not up...

Page 428: ...value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit no Bit symbol name Description 15 Un0DIR This bit is used to choose the communication direction in UARTn0 full duplex and half duplex mode 0 LSB first Initia...

Page 429: ...lock of baud rate generator in UARTn0 full duplex and half duplex mode 00 LSCLK initial value 01 Do not use LSCLK 10 HSCLK 11 Do not use HSCLK 0 Un0IO This bit is used to choose the transmission mode...

Page 430: ...R W R W R W R W R W R W R W R W R W R R R R R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit no Bit symbol name Description 15 Un1DIR This bit is used to choose the communication directi...

Page 431: ...the base clock of baud rate generator in UARTn1 half duplex mode 00 LSCLK initial value 01 Do not use LSCLK 10 HSCLK 11 Do not use HSCLK 0 Un1IO This bit is used to choose the transmission mode or re...

Page 432: ...1 1 1 1 1 1 1 1 1 11 2 11 UARTn1 Baud Rate Register UAn1BRT UAn1BRT is a specific function register SFR to set the count value of the baud rate generator in UARTn0 half duplex communication mode No n...

Page 433: ...0 0 0 0 0 0 0 0 0 11 2 13 UARTn1 Baud Rate Adjustment Register UAn1BRC UAn1BRC is a specific function register SFR to adjust the count value of the baud rate generator in UARTn1 half duplex communica...

Page 434: ...x communication mode is chosen this bit becomes 1 when transmission data is written to the SD0BUFH register and becomes 0 when the transmission data is transferred to the shift register To transmit da...

Page 435: ...RTn0 full duplex communication mode and half duplex communication mode This bit becomes 1 when an error occurs in the stop bit and holds 1 until it is cleared by the software The Un0FER bit is forcibl...

Page 436: ...uplex communication mode 0 Data transmission is stopped initial value 1 Data transmission is in progress 3 Un1FUL This bit is used to indicate the state of the transmit receive buffer in UARTn1 half d...

Page 437: ...Tn1 half duplex communication mode This bit becomes 1 when an error occurs in the stop bit and holds 1 until it is cleared by the software The Un1FER bit is forcibly reset to 0 by writing 1 to this bi...

Page 438: ...First Figure 11 3 Transmit Operation Waveforms of Synchronous Serial Port for Clock Type 0 Negative Logic 8 Bit Length LSB First Figure 11 4 Transmit Operation Waveforms of Synchronous Serial Port fo...

Page 439: ...L62Q1000 11 37 Figure 11 5 Transmit Operation Waveforms of Synchronous Serial Port for Clock Type 1 Negative Logic 8 Bit Length LSB First SnEN 0 1 2 3 4 5 7 6 Transmit data SUn_SCLK SDnBUF SUn_SOUT SI...

Page 440: ...rame interval at the time of reception use the transmission reception mode Figure 11 6 Receive Operation Waveforms of Synchronous Serial Port for Clock Type 0 Positive Logic 8 Bit Length MSB First Fig...

Page 441: ...ative Logic 8 Bit Length MSB First SnEN SUn_SCLK SUn_SIN Shift register SIUn0INT SUnRC0 0 7 6 5 4 3 2 1 Receive data 7 6 5 4 3 2 1 0 SnFUL SnRXF Write SDnBUF When an interrupt at the start of receptio...

Page 442: ...irst clock type 0 of the synchronous serial port Figure 11 10 Receive Operation Waveforms of Synchronous Serial Port for Clock Type 0 Positive Logic 16 Bit Length LSB First SnEN SUn_SCLK SUnRC1 0 SUn_...

Page 443: ...nsmission Reception The buffer has data The buffer has data The buffer has no data Both case At the start of transmission or at the end of reception The interval time is set The interval time is not s...

Page 444: ...a Data Data Data Data Data Data Data Data Transmission Reception At the start of transmission or reception The buffer has data The buffer has no data At the start of transmission or at the end of rece...

Page 445: ...ffer has data At the end of reception The buffer has no data Timing of the interrupt generation indicates the interrupt Transmission At the start of transmission The interval time is set The buffer ha...

Page 446: ...Serial Port in Clock Type 1 Positive Logic Slave Mode Note Even after the start interrupt has been generated it is possible to write data to the transfer buffer before the transfer is actually started...

Page 447: ...utput All of these are set in the UARTn mode register UAnMOD Figure 11 12 and Figure 11 13 show the positive logic input output format and negative logic input output format respectively Figure 11 12...

Page 448: ...gn with the central value Example Base clock frequency Approx 24 MHz 23 986176 MHz Baud rate 115 200 bps UAn0BRT 23 986176 MHz 115 200 bps 1 208 21333 1 207 rounding down to the nearest integer 0x00CF...

Page 449: ...035 0x05 299 99bps 1 200bps 0x340C 0x05 1200 00bps 2 400bps 0x1A05 0x07 2399 98bps 4 800bps 0x0D02 0x03 4800 05bps 9 600bps 0x0680 0x06 9599 75bps 19 200bps 0x033F 0x07 19199 50bps 38 400bps 0x019F 0x...

Page 450: ...SnB3 SnB7 SnB5 SnB2 SnB1 SnB4 SnB0 LSB transmission LSB reception When the data length is 8 bit length When the data length is 7 bit length When the data length is 6 bit length SnB7 is 0 when receptio...

Page 451: ...UAn0STAT to be set to 1 and the baud rate generator to generate the internal transfer clock Then the transmission is started Once the the transmission is started the start bit is output to the SUn_TXD...

Page 452: ...d rate generator starts generating the transfer clock When H level is received in the middle of the start bit it is recognized as an unintended operation and the detection of the start bit is resumed...

Page 453: ...n At the start of transmission The interval time is set The buffer has data The interval time is not set The buffer has data Both case The buffer has no data Timing of the interrupt generation indicat...

Page 454: ...ud rate then loaded to the shift register This sampling timing the shift register uses to load data can be adjusted for one clock of the baud rate generator clock in the Un0RSS bit of the UARTn mode r...

Page 455: ...When using the half duplex UART and changing the transmission mode to receive mode you must initialize and reconfigure the channel as the receive mode after reset the channel of serial communication...

Page 456: ...Chapter 12 I2 C Bus Unit...

Page 457: ...n product 100pin product 0 Available 12 1 1 Features Table 12 2 shows the features of I2 C bus unit Table 12 2 Features of I 2 C bus unit Function Operation mode Features I 2 C bus unit Master functio...

Page 458: ...0 control register master I2UM0STA I 2 C bus 0 status register master I2US0RD I 2 C bus 0 receive register slave I2US0SA I 2 C bus 0 slave address register slave I2US0TD I 2 C bus 0 transmit data reg...

Page 459: ...3 I 2 C bus unit general port combinations Port name PnMODm Combination Setting data ML62Q1300 group ML62Q1500 group ML62Q1700 group 16pin product 20pin product 24pin product 32pin product 48pin produ...

Page 460: ...2UM0CON R W 8 0x00 0xF6C9 Reserved R 8 0x00 0xF6CA I 2 C bus 0 mode register master I2UM0MDL I2UM0MOD R W 8 16 0x00 0xF6CB I2UM0MDH R W 8 0x02 0xF6CC I 2 C bus 0 status register master I2UM0STA I2UM0S...

Page 461: ...ct multiple master devices on the I 2 C bus If powering off this LSI in the slave mode it disables communications of other devices on the I2C bus Remain the power to this LSI when it works as a slave...

Page 462: ...UM0 R3 I2UM0 R2 I2UM0 R1 I2UM0 R0 R W R R R R R R R R R R R R R R R R Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit no Bit symbol name Description 7 to 0 I2UM0R7 to I2UM0R0 These bits are used to...

Page 463: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word Byte I2UM0SA Bit I2UM0 A6 I2UM0 A5 I2UM0 A4 I2UM0 A3 I2UM0 A2 I2UM0 A1 I2UM0 A0 I2UM0 RW R W R R R R R R R R R W R W R W R W R W R W R W R W Initial value 0...

Page 464: ...dress 0xF6C6 I2UM0TD Access R W Access size 8bit Initial value 0x00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word Byte I2UM0TD Bit I2UM0 T7 I2UM0 T6 I2UM0 T5 I2UM0 T4 I2UM0 T3 I2UM0 T2 I2UM0 T1 I2UM0 T0...

Page 465: ...ve I2UM0ST 1 The I2UM0RS bit always returns 0 for reading 0 No restart request initial value 1 Restart request 1 I2UM0SP This bit is a write only and used to request a stop condition in the master mod...

Page 466: ...for details of the communication speed and clock counts 7 6 Reserved bit 5 I2UM0SYN This bit is used to choose whether to or not to use the clock stretch handshake function in the master mode Set this...

Page 467: ...nitialized In the case 0 is written to this bit during the communication initialize the I 2 C bus unit and reconfigure it 0 Stop the I 2 C master operation initial value 1 Enable the I 2 C master oper...

Page 468: ...completed 8 I2UM0AS This bit is used to indicate the usage state of the I 2 C bus in the master mode This bit is set to 1 when transmitting the start condition and 7 bit slave address have been comple...

Page 469: ...bit is reset to 0 0 Received acknowledgment 0 initial value 1 Received acknowledgment 1 0 I2UM0BB This bit is used to indicate the usage state of the I2C bus in the master mode When the start conditi...

Page 470: ...R5 I2US0 R4 I2US0 R3 I2US0 R2 I2US0 R1 I2US0 R0 R W R R R R R R R R R R R R R R R R Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit no Bit symbol name Description 7 to 0 I2US0R7 to I2US0R0 These bit...

Page 471: ...ess 0xF6D0 I2US0SA Access R W Access size 8bit Initial value 0x00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word Byte I2US0SA Bit I2US0A 6 I2US0A 5 I2US0A 4 I2US0A 3 I2US0A 2 I2US0A 1 I2US0A 0 R W R R R R...

Page 472: ...dress 0xF6D2 I2US0TD Access R W Access size 8bit Initial value 0x00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word Byte I2US0TD Bit I2US0T 7 I2US0T 6 I2US0T 5 I2US0T 4 I2US0T 3 I2US0T 2 I2US0T 1 I2US0T 0...

Page 473: ...0ACT This bit is used to set the acknowledgment data to be output at completion of reception in the slave mode 0 Acknowledgment data 0 initial value 1 Acknowledgment data 1 6 Reserved bit 5 I2US0WT Th...

Page 474: ...pt after the restart condition 3 I2US0NAL This bit is used to enable or disable the communication wait function of the I 2 C bus unit output L level on the I2CU0_SCL pin when transmitting to the maste...

Page 475: ...e start condition To reset the I2US0STS bit write 1 to this bit or write 0 to I2US0EN bit of I2US0MD register 0 The start condition has not been received Initial value 1 The start condition has been r...

Page 476: ...When the value of the bit transmitted and the value of the I2CU0_SDA pin do not coincide this bit is set to 1 When this bit is set to 1 the I2CU0_SDA pin output is disabled until the subsequent byte...

Page 477: ...condition Set I2UM0EN 1 in the I2UM0MOD register Initial setting start Set communication mode Set I2UM0A6 to I2UM0A0 bits and I2UM0RW bit in the I2UM0SA register Select master mode Set I2UMD 0 in the...

Page 478: ...ss transmit mode completed move to control register setting wait state Slave address transmit mode Acknowledgment signal is received by I 2 C bus 0 status register I2UM0STA Acknowledgment signal is re...

Page 479: ...ode Only when operation mode is changed Set I2UM0MOD register Set control register Set the I2UM0CON register I2UM0ST bit Starts communication I2UM0ST 1 I2UM0SP bit Stop condition request I2UM0SP 1 I2U...

Page 480: ...to I2CU0_SDA pin is stored in synchronization with rising edge of transfer clock input to I2CU0_SCL pin in MSB first I 2 C bus 0 control register I2UM0CON setting wait state Store data in I 2 C bus 0...

Page 481: ...A 6 A 5 A 4 A 3 A 2 A 1 A 0 R W A D 6 D 0 D 7 A D 6 D 7 D 0 A D 6 D 7 D 0 A P I2UM0CON 02H Values of I2UM0TD 3 Values of I2UM0TD 1 Values of I2UM0SA Register setting I2CU0_SDA pin I2CU0INT I2UM0ST bit...

Page 482: ...output is disabled until termination of the subsequent byte data communication Figure 12 6 shows the operation timing and control method when transmission fails Figure 12 6 Operation timing when trans...

Page 483: ...S0MD register I2US0SIE bit Enable disable start condition interrupt I2US0PIE bit Enable disable stop condition interrupt Select slave mode Select I2U0MD 1 in the I2U0MSS register Set I 2 C bus 0 mode...

Page 484: ...h rising edge of transfer clock input to I2CU0_SCL pin in MSB first Transmit acknowledgment data Acknowledgment data L level is output Compare slave address stored in shift register with slave address...

Page 485: ...it Write data transmitted next time Only when data is transmitted Set the I2US0TD register I2US0T7 to I2US0T0 bits 8 bit transmit data Generate I 2 C bus unit interrupt I2CU0INT When entering communic...

Page 486: ...ge of transfer clock input to I2CU0_SCL pin in MSB first Shift to communication wait state after detection of falling edge of transfer clock which was input to I2CU0_SCL pin transmitting acknowledgmen...

Page 487: ...A P I2US0CON 20H Received data 3 Received data 1 Slave address Slave address Register setting I2CU0_SDA pin I2CU0INT I2US0SAA bit I2US0RD register I2US0TR bit I2US0TD xxH I2US0CON 20H I2US0TD xxH I2US...

Page 488: ...munication Figure 12 10 shows the operation timing and control method when transmission fails Figure 12 10 Operation Timing When Transmission Fails When Slave Mode is Chosen Note If entering to the ST...

Page 489: ...400 kbps 00 no reduction 60 24 36 12 24 36 24 24 36 01 10 reduction 66 27 39 12 27 39 27 27 39 10 20 reduction 72 30 42 12 30 42 30 30 42 11 30 reduction 78 33 45 12 33 45 33 33 45 10 or 11 1 Mbps mo...

Page 490: ...s increase in proportion to the dividing ratio When using the high speed clock for the I2C operation specify the following I2C operating clock frequency depending on the mode and the reference frequen...

Page 491: ...Chapter 13 I2 C Master...

Page 492: ...ML62Q1300 group ML62Q1500 ML62Q1700 group 16pin product 20pin product 24pin product 32pin product 48pin Product 52pin product 64pin product 80pin product 100pin product 0 1 Available Unavailable 13 1...

Page 493: ...CMn_SDA Serial Data I2MnRD I 2 C master n receive register I2MnSA I 2 C master n slave address register I2MnTD I 2 C master n transmit data register I2MnCON I 2 C master n control register I2MnMOD I 2...

Page 494: ...hared function choose Enable Input Enable Output Nch open drain output and without pull up by setting following data to the port n mode register m PnMODm Table 13 3 I 2 C bus master general port combi...

Page 495: ...x00 0xF6EA I 2 C master 0 mode register I2M0MODL I2M0MOD R W 8 16 0x00 0xF6EB I2M0MODH R W 8 0x02 0xF6EC I 2 C master 0 status register I2M0STAT I2M0STR R W 8 16 0x00 0xF6ED I2M0ISR R W 8 0x00 0xF6F0...

Page 496: ...MnR 3 I2MnR 2 I2MnR 1 I2MnR 0 R W R R R R R R R R R R R R R R R R Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit symbol name Description 7 to 0 I2MnR7 to I2MnR0 These bits are used to store...

Page 497: ...t Initial value 0x00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word Byte I2MnSA Bit I2MnA 6 I2MnA 5 I2MnA 4 I2MnA 3 I2MnA 2 I2MnA 1 I2MnA 0 I2MnR W R W R R R R R R R R R W R W R W R W R W R W R W R W Init...

Page 498: ...ess 0xF6E6 I2M0TD 0xF6F6 I2M1TD Access R W Access size 8bit Initial value 0x00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word Byte I2MnTD Bit I2MnT 7 I2MnT 6 I2MnT 5 I2MnT 4 I2MnT 3 I2MnT 2 I2MnT 1 I2MnT...

Page 499: ...request initial value 1 Restart request 1 I2MnSP This bit is a write only and used to request a stop condition When 1 is written to this bit the LSI shifts to the stop condition and the communication...

Page 500: ...er depending on the load of I 2 C bus 0 Not use the clock stretch function Initial value 1 Use the clock stretch function 4 3 I2MnDW1 I2MnDW0 These bits are used to set the communication speed reducti...

Page 501: ...peration specify the following I 2 C operating clock frequency depending on the mode and the reference frequency of the PLL oscillation When HSCLK 24MHz Standard mode HSCLK to 1 4HSCLK Fast mode HSCLK...

Page 502: ...tial value 1 The transmission reception has been completed 8 I2MnAS This bit is used to indicate the usage state of the I 2 C bus This bit is set to 1 when transmitting the start condition and 7 bit s...

Page 503: ...d When 1 is written to this bit this bit is reset to 0 0 Received acknowledgment 0 initial value 1 Received acknowledgment 1 0 I2MnBB This bit is used to indicate the usage state of the I2C bus When t...

Page 504: ...Set I2MnEN 1 in the I2MnMOD register Initial setting start Enable operation of I2C function Set the I2MnSA register I2MnA6 to I2MnA0 bits Set slave address I2MnRW Set data direction transmission recep...

Page 505: ...tion I2MnST 1 Slave address transmit mode completed move to control register setting wait state Slave address transmit mode Acknowledgment signal is received by I 2 C Acknowledgment signal is received...

Page 506: ...de is changed Set the I2MnMOD register Set communication mode through each bit Set I 2 C master 0 control register Set I2MnCON register I2MnST bit Starting communication I2MnST 1 I2MnSP bit Stop condi...

Page 507: ...tored in synchronization with rising edge of transfer clock input to I2CMn_SCL pin in MSB first I 2 C master 0 control register I2MnCON setting wait state Store data in I 2 C master 0 receive register...

Page 508: ...TD 3 Values of I2MnTD 1 Values of I2MnSA Values of I2MnSA Register setting I2CMn_SDA pin I2MnINT I2MnST bit I2MnRD register I2MnSA xxxxxxx1B I2MnCON 01H I2MnCON 01H I2MnCON 01H I2MnCON 81H Received da...

Page 509: ...SDA pin output is disabled until termination of the subsequent byte data communication Figure 13 6 shows the operation timing and control method when transmission fails Figure 13 6 Operation timing wh...

Page 510: ...eduction 66 27 39 12 27 39 27 27 39 10 20 reduction 72 30 42 12 30 42 30 30 42 11 30 reduction 78 33 45 12 33 45 33 33 45 10 or 11 1 Mbps mode 1 Mbps 00 no reduction 24 10 14 4 10 14 10 10 14 01 10 re...

Page 511: ...or 11 1 Mbps mode 1 Mbps 00 no reduction 16 6 10 4 6 10 6 6 10 01 10 reduction 18 7 11 4 7 11 7 7 11 10 20 reduction 19 8 11 4 8 11 7 8 11 11 30 reduction 21 9 12 4 9 12 8 9 12 The above clock counts...

Page 512: ...Chapter 14 DMA Controller...

Page 513: ...without the CPU operation Table 14 1 in the section 14 3 5 DMA Transfer Target Block shows available peripheral bocks to use as the DMA transfer source or destination Figure 14 1 DMA Controller Overvi...

Page 514: ...s Increment address Decrement address Transfer target SFR RAM Transfer from to Flash is not supported Transfer trigger Serial communication DMA request Successive approximation type A D DMA request 16...

Page 515: ...r destination address register DCEN DMA transfer enable register n 0 1 Figure 14 2 Configuration of DMA Controller Circuit Data bus Transfer request Register DCnMODL Transfer source destination addres...

Page 516: ...tion address register DC0DAL DC0DA R W 8 16 0x00 0xF707 DC0DAH R W 8 0x00 0xF708 DMA channel 1 transfer mode register DC1MODL DC1MOD R W 8 16 0x00 0xF709 DC1MODH R W 8 0x00 0xF70A DMA channel 1 transf...

Page 517: ...ware trigger 14 13 Reserved 12 to 8 DCnTRG4 to DCnTRG0 These bits are used to choose the DMA transfer trigger of channel n 00000 No DMA request initial value 00001 Successive approximation type A D DM...

Page 518: ...sed to set the addressing mode of the transfer source of channel n 00 Fixed address mode initial value The transfer source address or transfer destination address is fixed 01 Increment address mode DC...

Page 519: ...to set the transfer count for channel n The transfer count can be set to between 1 and 1024 As the transfer count is decremented every DMA transfer the rest of the transfer counts can be checked by re...

Page 520: ...The lowest bit is ignored d0 0 and even numbered addresses become the targets in the 16 bit data transfer Address 0xF704 DC0SAL DC0SA 0xF705 DC0SAH 0xF70C DC1SAL DC1SA 0xF70D DC1SAH Access R W Access...

Page 521: ...sfer The lowest bit is ignored d0 0 and even numbered addresses become the targets in the 16 bit data transfer Address 0xF706 DC0DAL DC0DA 0xF707 DC0DAH 0xF70E DC1DAL DC1DA 0xF70F DC1DAH Access R W Ac...

Page 522: ...gger is generated on both at the same time channel 0 has the priority 0 DMA transfer channel is free initial value 1 DMA transfer channel is fixed 6 to 2 Reserved bit 1 0 DC1EN DC0EN These bits are us...

Page 523: ...tion 15 to 11 Reserved bit 9 8 DCnSTA n 1 0 These bits indicate that channel n is transferring in the transfer channel fixed mode DCF bit of DCEN register is 1 These bits are fixed to 0 in the transfe...

Page 524: ...R 1 DICLR 0 R W R R R R R R R R R R R R R R W W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit symbol name Description 7 to 2 Reserved bit 1 DICLR1 DC1ISTA bit of DSTATL register is cleared...

Page 525: ...imes Set with DCnSAMD0 and DCnSAMD1 bits of the DCnMOD register Select the address fixed mode increment addressing mode or decrement addressing mode Set with the DCnSA register Initialize the peripher...

Page 526: ...controller termination procedure Figure 14 4 DMA Termination Procedure n 0 or 1 End Set with the EDMA bit EDMA 0 Write 1 to the DICLRn bit of the DICLR register Confirm transfer status Confirm operati...

Page 527: ...unit 8 bit transfer count twice Note CPU data memory access is processed in priority to the DMA transfer Successive CPU data memory access may cause the DMA transfer to be held resulting in the trans...

Page 528: ...transfer count reaches the remaining 0 Transfer mode setting Transfer count setting DMA interrupt generated after transfer is completed DMA transfer enable Interrupt status clear DICLR1 1 EDMA 0 DMA...

Page 529: ...the transfer count reaches the remaining 0 Transfer mode setting Transfer count setting DMA interrupt generated after transfer is completed DMA transfer enable Interrupt status clear DICLR1 1 EDMA 0 D...

Page 530: ...h Multiplier Divider Reset Functions Power management Interrupt Clock Generation Circuit Time base counter 16 bit timer Functional timer Watchdog timer Serial communication unit I 2 C bus unit I 2 C b...

Page 531: ...Chapter 15 Buzzer...

Page 532: ...ative phase pulise BZ0N The buzzer output function is assigned to the shared function of the general ports See Chapter 17 GPIO for details about the assignment Also for details of the clock used in th...

Page 533: ...sound 1 Intermittent sound 2 Single sound and Continuous sound Eight frequencies 4 096 kHz to 293 Hz 15 duties 1 16 to 15 16 6 25 to 93 75 Only seven duties 1 8 to 7 8 are available when the buzzer fr...

Page 534: ...the buzzer circuit BZ0CON Buzzer 0 control register BZ0MOD Buzzer 0 mode register Figure 15 2 Configuration of Buzzer Data bus Buzzer output mode choice circuit Frequency choise Duty choice mode choic...

Page 535: ...the buzzer and the register settings ML62Q1700 group Pin name Shared pin Setting register Setting value BZ0P P17 7 th Function P1MOD7 0110_XXXX P26 7 th Function P2MOD6 0110_XXXX BZ0P P20 7 th Functio...

Page 536: ...15 2 Description of Registers 15 2 1 List of Registers Address Name Symbol R W Size Initial Value Byte Word 0xF0C0 Buzzer 0 control register BZ0CON R W 8 0x00 0xF0C1 Reserved 8 0x00 0xF0C2 Buzzer 0 mo...

Page 537: ...5 4 3 2 1 0 Word Byte BZ0CON Bit BZ0RU N R W R R R R R R R R R R R R R R R R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit symbol name Description 15 to 1 Reserved bit 0 BZ0RUN This bit...

Page 538: ...the buzzer sound changes by changing the duty Buzzer Frequency 4 096kHz Buzzer Frequency other than 4 096kHz 0000 Duty is 1 8 12 5 Initial Duty is 1 16 6 25 Initial small 0001 Duty is 1 8 12 5 Duty is...

Page 539: ...00 Intermittent sound 1 output mode initial value Sound like Beep Beep Beep Beep Beep Beep Beep Beep 01 Intermittent sound 2 output mode Sound like Beep Beep Beep Beep 10 Single sound mode Sound like...

Page 540: ...tent Sound 1 Mode Setting Procedure Figure 15 4 shows an example of the intermittent sound 1 mode setting procedure Figure 15 4 Example of Intermittent Sound 1 Mode Setting Procedure BZ0RUN T8HZ Buzze...

Page 541: ...timing the BZ0RUN bit of the BZ0CON register is set to 1 If it causes a problem take one of the following measure A or measure B Measure A Use the low speed time base counter interrupt choose T8HZ or...

Page 542: ...zer waveform depending on timing the BZ0RUN bit of the BZ0CON register is set to 1 If it causes a problem take one of the following measures A or B described below Measure A Use the low speed time bas...

Page 543: ...of the BZ0CON register is set to 1 If it causes a problem take one of the following measures A or B described below Measure A Use the low speed time base counter interrupt choose T8HZ or T1HZ for sign...

Page 544: ...und Mode Setting Procedure Figure 15 10 shows an example of the continuous sound mode setting procedure Figure 15 10 Example of Continuous Sound Mode Setting Procedure Buzzer output waveform BZ0P and...

Page 545: ...zer output is started after writing 1 to the BZ0RUN bit of the BZ0CON register 1 When positive logic is applied BZ0INI bit of BZ0MOD register 0 Setting example buzzer frequency 4 096 kHz duty 3 8 37 5...

Page 546: ...the buzzer output is stopped after writing 0 to the BZ0RUN bit of the BZ0CON register BZ0RUN 1 When positive logic is applied BZ0INI bit of BZ0MOD register 0 Setting example buzzer frequency 4 096 kH...

Page 547: ...to 0 when the single sound buzzer output is ended BZ0RUN 1 When positive logic is applied BZ0INI bit of BZ0MOD register 0 Setting example buzzer frequency 4 096 kHz duty 3 8 37 5 LSCLK 32 768 kHz BZ0...

Page 548: ...it 1 When positive logic is applied BZ0INI bit of BZ0MOD register 0 Setting example buzzer frequency 4 096 kHz duty 3 8 37 5 LSCLK 32 768 kHz BZ0P pin BZ0N pin 4 096kHz 2 When negative logic is applie...

Page 549: ...d clock LSCLK occurs by the time the buzzer output is started after the T8HZ signal became 1 T8HZ bit 1 When positive logic is applied BZ0INI bit of BZ0MOD register 0 Setting example buzzer frequency...

Page 550: ...Chapter 16 Simplified RTC...

Page 551: ...ired periodical interrupt request can be chosen from among four types 0 5 1 30 and 60 seconds Counting operation is continued all the time except when operating in the STOP STOP D mode A function to p...

Page 552: ...W Size Initial value Byte Word 0xF0C8 Simplified RTC acceptor SRTCACP W 8 0x00 0xF0C9 Reserved register R 8 0x00 0xF0CA Simplified RTC minute second counter SRTCSEC SRTCMAS R W 8 16 0x00 0xF0CB SRTCM...

Page 553: ...the SRTCMAS register is enabled only once Address 0xF0C8 SRTCACP Access W Access size 8 bits Initial value 0x00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word Byte SRTCACP Bit rd7 rd6 rd5 rd4 rd3 rd2 rd1...

Page 554: ...icate the simplified RTC operating status The initial value of PORSTAT bit is 1 To write data to the SRTCMAS register write 0 to the PORSTAT bit When 1 is written to the PORSTAT bit the initial value...

Page 555: ...g generated while writing time data disable the periodical interrupt request using the simplified RTC control register SRTCCON before writing to the SRTCMAS register It is recommended that data is wri...

Page 556: ...nitial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit symbol name Description 15 to 3 Reserved bits 2 to 0 RINT2 to RINT0 Bits to set a periodical interrupt request 000 Periodical interrupt request...

Page 557: ...peration is continued when any other system resets occur Table 16 1 shows a list of count values of each counter Table 16 2 Count Value of Each Counter Counter name Count value Second counter SRTCSEC4...

Page 558: ...seconds to the SRTCMAS register Figure 16 3 Simplified RTC Setting Example for Writing Time Data Setting start SRTCCON setting SRTCACP setting Write to SRTCMAS SRTCCON setting Setting completed Set t...

Page 559: ...Chapter 17 GPIO...

Page 560: ...h the max eight pins and the input and output is switchable on each pin The general input output ports can be used for external interrupts and external inputs for the functional timers Also used as an...

Page 561: ...ut or output can be chosen in each pin Pull up resister can be chosen in each pin CMOS output or N channel open drain output is can be chosen in each pin Direct driving LEDs is supported when the N ch...

Page 562: ...9 A B in the case of PnMOD45 and PnMOD67 Figure 17 1 Configuration of General Purpose I O port n PXT0DI PADXT0 data input register PXT1DI PADXT1 data input register PXTMOD01 PADXT0 1 mode register01 F...

Page 563: ...pin product 100pin product PI00 Crystal resonator conenction pin PI01 Crystal resonator conenction pin P00 I O port P01 I O port DACOUT0 P02 I O port EXI0 P03 I O port EXI1 P04 I O port EXI2 P05 I O p...

Page 564: ...I O port P43 I O port P44 I O port DACOUT1 P45 I O port P46 I O port P47 I O port P50 I O port EXI8 P51 I O port P52 I O port P53 I O port P54 I O port P55 I O port P56 I O port P57 I O port P60 I O...

Page 565: ...oduct 80pin product 100pin product P85 I O port P86 I O port P87 I O port P90 I O port P91 I O port P92 I O port P93 I O port P94 I O port P95 I O port P96 I O port P97 I O port PA0 I O port PA1 I O p...

Page 566: ...data register P1DI P1D R W 8 16 0xFF 0xF211 P1DO R W 8 0x00 0xF212 Port 1 mode register 01 P1MOD0 P1MOD01 R W 8 16 0x00 0xF213 P1MOD1 R W 8 0x00 0xF214 Port 1 mode register 23 P1MOD2 P1MOD23 R W 8 16...

Page 567: ...P3PSLL P3PSL R W 8 16 0x00 0xF23D P3PSLH R W 8 0x00 0xF23E Reserved R 8 0x00 0xF23F R 8 0x00 0xF240 Port 4 data register P4DI P4D R W 8 16 0xFF 0xF241 P4DO R W 8 0x00 0xF242 Port 4 mode register 01 P4...

Page 568: ...275 P7MOD3 R W 8 0x00 0xF276 Port 7 mode register 45 P7MOD4 P7MOD45 R W 8 16 0x00 0xF277 P7MOD5 R W 8 0x00 0xF278 Port 7 mode register 67 P7MOD6 P7MOD67 R W 8 16 0x00 0xF279 P7MOD7 R W 8 0x00 0xF27A t...

Page 569: ...register 67 PAMOD6 PAMOD67 R W 8 16 0x00 0xF2A9 PAMOD7 R W 8 0x00 0xF2AA to 0xF2AF Reserved R 8 0x00 0xF2B0 Port B data register PBDI PBD R W 8 16 0xFF 0xF2B1 PBDO R W 8 0x00 0xF2B2 Port B mode regist...

Page 570: ...0 P01 P01DO P01DI P0MOD1 P02 P02DO P02DI P0MOD2 P03 P03DO P03DI P0MOD3 P03PLVL P03PEN P03PSL P04 P04DO P04DI P0MOD4 P05 P05DO P05DI P0MOD5 P06 P06DO P06DI P0MOD6 P07 P07DO P07DI P0MOD7 Port 1 P10 P10D...

Page 571: ...P42 P42DO P42DI P4MOD2 P43 P43DO P43DI P4MOD3 P44 P44DO P44DI P4MOD4 P45 P45DO P45DI P4MOD5 P46 P46DO P46DI P4MOD6 P47 P47DO P47DI P4MOD7 Port 5 P50 P50DO P50DI P5MOD0 P51 P51DO P51DI P5MOD1 P52 P52D...

Page 572: ...85DO P85DI P8MOD5 P86 P86DO P86DI P8MOD6 P87 P87DO P87DI P8MOD7 Port 9 P90 P90DO P90DI P9MOD0 P91 P91DO P91DI P9MOD1 P92 P92DO P92DI P9MOD2 P93 P93DO P93DI P9MOD3 P94 P94DO P94DI P9MOD4 P95 P95DO P95D...

Page 573: ...xF201 P0DO 0xF210 P1DI P1D 0xF211 P1DO 0xF220 P2DI P2D 0xF221 P2DO 0xF230 P3DI P3D 0xF231 P3DO 0xF240 P4DI P4D 0xF241 P4DO 0xF250 P5DI P5D 0xF251 P5DO 0xF260 P6DI P6D 0xF261 P6DO 0xF270 P7DI P7D 0xF27...

Page 574: ...5 4 3 2 1 0 Word PnMOD01 Byte PnMOD1 PnMOD0 Bit Pn1MD 3 Pn1MD 2 Pn1MD 1 Pn1MD 0 Pn1OD Pn1PU Pn1OE Pn1IE Pn0MD 3 Pn0MD 2 Pn0MD 1 Pn0MD 0 Pn0OD Pn0PU Pn0OE Pn0IE R W R W R W R W R W R W R W R W R W R W...

Page 575: ...t Table 1 8 ML62Q1500 Group Pin List and Table 1 9 ML62Q1700 Group Pin List 0000 Primary function initial value 0001 2 nd function 0010 3 rd function 0011 4 th function 0100 5 th function 0101 6 th fu...

Page 576: ...the PnMODm n 0 to B m 0 to 7 registers before setting EICON0 EIMOD0 and IE1 registers If setting the PnMODm register when the interrupt is enabled unexpected interrupts may happen Enable the output b...

Page 577: ...lue 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word PnMOD23 Byte PnMOD3 PnMOD2 Bit Pn3MD 3 Pn3MD 2 Pn3MD 1 Pn3MD 0 Pn3OD Pn3PU Pn3OE Pn3IE Pn2MD 3 Pn2MD 2 Pn2MD 1 Pn2MD 0 Pn2OD Pn2PU Pn2OE Pn2IE R W...

Page 578: ...t Table 1 8 ML62Q1500 Group Pin List and Table 1 9 ML62Q1700 Group Pin List 0000 Primary function initial value 0001 2 nd function 0010 3 rd function 0011 4 th function 0100 5 th function 0101 6 th fu...

Page 579: ...the PnMODm n 0 to B m 0 to 7 registers before setting EICON0 EIMOD0 and IE1 registers If setting the PnMODm register when the interrupt is enabled unexpected interrupts may happen Enable the output b...

Page 580: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word PnMOD45 Byte PnMOD5 PnMOD4 Bit Pn5MD 3 Pn5MD 2 Pn5MD 1 Pn5MD 0 Pn5OD Pn5PU Pn5OE Pn5IE Pn4MD 3 Pn4MD 2 Pn4MD 1 Pn4MD 0 Pn4OD Pn4PU Pn4OE Pn4IE R W R W R W R W R...

Page 581: ...t Table 1 8 ML62Q1500 Group Pin List and Table 1 9 ML62Q1700 Group Pin List 0000 Primary function initial value 0001 2 nd function 0010 3 rd function 0011 4 th function 0100 5 th function 0101 6 th fu...

Page 582: ...the PnMODm n 0 to B m 0 to 7 registers before setting EICON0 EIMOD0 and IE1 registers If setting the PnMODm register when the interrupt is enabled unexpected interrupts may happen Enable the output b...

Page 583: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word PnMOD67 Byte PnMOD7 PnMOD6 Bit Pn7MD 3 Pn7MD 2 Pn7MD 1 Pn7MD 0 Pn7OD Pn7PU Pn7OE Pn7IE Pn6MD 3 Pn6MD 2 Pn6MD 1 Pn6MD 0 Pn6OD Pn6PU Pn6OE Pn6IE R W R W R W R W R...

Page 584: ...t Table 1 8 ML62Q1500 Group Pin List and Table 1 9 ML62Q1700 Group Pin List 0000 Primary function initial value 0001 2 nd function 0010 3 rd function 0011 4 th function 0100 5 th function 0101 6 th fu...

Page 585: ...the PnMODm n 0 to B m 0 to 7 registers before setting EICON0 EIMOD0 and IE1 registers If setting the PnMODm register when the interrupt is enabled unexpected interrupts may happen Enable the output b...

Page 586: ...L VL Pn6PL VL Pn5PL VL Pn4PL VL Pn3PL VL Pn2PL VL Pn1PL VL Pn0PL VL Pn7PE N Pn6PE N Pn5PE N Pn4PE N Pn3PE N Pn2PE N Pn1PE N Pn0PE N R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W...

Page 587: ...2D P2PSH 0xF23C P3PSLL P3PSL 0xF23D P3PSH Access R W Access size 8 16bit Initial value 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word PnPSL Byte PnPSLH PnPSLL Bit Pn7PS L Pn6PS L Pn5PS L Pn4PS L Pn...

Page 588: ...T0D I R W R R R R R R R R R R R R R R R R Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 undefin ed undefin ed Bit No Bit symbol name Description 7 to 2 Reserved bit 1 PXT1DI This bit is used for reading t...

Page 589: ...MOD1 Access R W Access size 8bit 16bit Initial value 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word PXTMOD01 Byte PXTMOD1 PXTMOD0 Bit PXT1IE PXT1I E R W R R R R R R R R W R R R R R R R R W Initial...

Page 590: ...are selected as the initial status n Port number 0 to 9 A B m Bit number 0 to 7 17 3 3 Primary Functions Other than Input Output Function External input EXI0 to EXI11 can be used as the primary funct...

Page 591: ...Pin P03PEN bit of P3PMD register 1 P03PLVL bit 0 Figure 17 4 Example of Carrier Frequency Output When P03 Pin is Assigned to UART Output Pin P03PEN bit of P3PMD register 1 P03PLVL bit 1 17 3 5 2 Carri...

Page 592: ...o the port n Port number 0 to 9 A B m Bit number 0 to 7 17 3 7 Port Setting Example Figure 17 6 shows an example for setting port registers to output 0x55 to a port Enable the output by setting the po...

Page 593: ...e 17 7 P00 TEST0 pin setting when releasing the RESET_N pin to H level 17 3 8 2 When using the On chip debug function and ISP function When using the on chip debug function or ISP function P00 TEST0 i...

Page 594: ...Chapter 18 External Interrupt Function...

Page 595: ...upt function generates interrupts by signals input to the general ports The interrupt channel has each dedicated interrupt vector For details of the interrupt vector see Chapter 5 Interrupt The number...

Page 596: ...vector is shared for four external input pins Expanded external interrupt Available to choose the interrupt mode interrupt disabled mode falling edge interrupt mode rising edge interrupt mode or both...

Page 597: ...e Register 1 EEISTAT Expanded External Interrupt Status Register EEINTC Expanded External Interrupt Clear Register Figure 18 2 Configuration of Expanded External Interrupt Function EXI8 to EXI11 Data...

Page 598: ...nal interrupt Table 18 1 shows the list of the general ports used for the external interrupt and the register settings of the ports Table 18 1 Ports used for the external interrupt and the register se...

Page 599: ...0 0xF0E2 Reserved R 8 0x00 0xF0E3 Reserved R 8 0x00 0xF0E4 Expanded external interrupt control register 0 1 EEICON0L EEICON0 R W 8 16 0x00 0xF0E5 EEICON0H R W 8 0x00 0xF0E6 Reserved R 8 0x00 0xF0E7 Re...

Page 600: ...0E0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit symbol name Description 15 to 8 PI7E1 to PI0E1 These bits are used to c...

Page 601: ...choose frequency dividing ratio for the sampling clock in the EXI0 to EXI7 000 No dividing Initial value 001 1 2 of the sampling clock source 010 1 4 of the sampling clock source 011 1 8 of the sampli...

Page 602: ...k is dependent of the clock or register settings For details about it see Table 4 5 Wake up Time from Standby Mode in the Chapter 4 Power Management When the HSCLK is chosen and ENOSC bit of FCON regi...

Page 603: ...W R R R R R W R W R W R W R R R R R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit symbol name Description 15 to 12 7 to 4 Reserved bit 11 to 8 EPI3E1 to EPI0E1 These bits are...

Page 604: ...0 Byte EEIMOD0H EEIMOD0L Bit EPI3S M EPI2S M EPI1S M EPI0S M R W R R R R R R R R R R R R R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit symbol name Description 15 to 4 Reserv...

Page 605: ...ock in the EXI8 to EXI11 000 No dividing Initial value 001 1 2 of the sampling clock source 010 1 4 of the sampling clock source 011 1 8 of the sampling clock source 100 1 16 of the sampling clock sou...

Page 606: ...7 6 5 4 3 2 1 0 Word EEISTAT Byte EEISTATH EEISTATL Bit EEI3S EEI2S EEI1S EEI0S R W R R R R R R R R R R R R R R R R Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit symbol name Description 15...

Page 607: ...CH EEINTCL Bit EEIR EEI3C EEI2C EEI1C EEI0C R W W R R R R R R R R R R R W W W W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit symbol name Description 15 EEIR This bit indicates the request...

Page 608: ...ng Generation timing No Generated in synchronization with system clock Yes Generated in synchronization with system clock after coincidence determined three times 2 1 The detection edge can be chosen...

Page 609: ...trigger signals EXTRG0 to EXTRG7 for the 16 bit timer and function timer In addition the sampling function contained in the external interrupt function can be used Figure 18 5 shows the external trigg...

Page 610: ...ired if using HSCLK for the sampling clock Setting start Set ports to the input mode in PnMODxx registers xx 01 23 45 67 End Enable the external interrupt in IE01 register Execute the EI instruction t...

Page 611: ...rence Set a detection edge for the extended external register in EEICON0 register Set sampling Choose with sampling in EEIMOD0L register EEIMOD0L 0x0F Set a dividing ratio of the sampling clock in the...

Page 612: ...Chapter 19 CRC Generator...

Page 613: ...lation mode to check data in program memory available in HALT mode or HALT H mode Figure 19 1 CRC generator overview Calculation Result Register CRC generator Arithmetic control Mode control Data inpu...

Page 614: ...alculation register by the software Calculation unit is 8bit Automatic CRC generation mode Automatic CRC calculation by the hardware to check data in program memory in HALT or HALT H mode and generate...

Page 615: ...alculation Start Segment Setting Register CRCESEG Automatic CRC Calculation End Segment Setting Register CRCSAD Automatic CRC Calculation Start Address Setting Register CRCEAD Automatic CRC Calculatio...

Page 616: ...n End Address Setting Register CRCEADL CRCEAD R W 8 16 0xFC 0xF0D3 CRCEADH R W 8 0xFF 0xF0D4 Automatic CRC Calculation Start Segment Setting Register CRCSSEG R W 8 0x00 0xF0D5 Reserved R 8 0x00 0xF0D6...

Page 617: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word CRCSAD Byte CRCSADH CRCSADL Bit CRCS AD15 CRCS AD14 CRCS AD13 CRCS AD12 CRCS AD11 CRCS AD10 CRCS AD9 CRCS AD8 CRCS AD7 CRCS AD6 CRCS AD5 CRCS AD4 CRCS AD3 CRCS...

Page 618: ...CRCEADL Bit CRCE AD15 CRCE AD14 CRCE AD13 CRCE AD12 CRCE AD11 CRCE AD10 CRCE AD9 CRCE AD8 CRCE AD7 CRCE AD6 CRCE AD5 CRCE AD4 CRCE AD3 CRCE AD2 R W R W R W R W R W R W R W R W R W R W R W R W R W R W...

Page 619: ...code area set in this register is incremented during the automatic CRC calculation mode Address 0xF0D4 Access R W Access size 8bit Initial value 0x00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word Byte C...

Page 620: ...of automatic CRC calculation Address 0xF0D6 Access R W Access size 8bit Initial value 0xFF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word Byte CRCESEG Bit CRCE SEG3 CRCE SEG2 CRCE SEG1 CRCE SEG0 R W R R R...

Page 621: ...ed in the CRC Calculation Result Register CRCRES Address 0xF0D8 Access R W Access size 8bit Initial value 0x00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word Byte CRCDATA Bit CRCD ATA7 CRCD ATA6 CRCD ATA5...

Page 622: ...cess size 8 16bit Initial value 0xFFFF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word CRCRES Byte CRCRESH CRCRESL Bit CRCR ES15 CRCR ES14 CRCR ES13 CRCR ES12 CRCR ES11 CRCR ES10 CRCR ES9 CRCR ES8 CRCR ES7...

Page 623: ...the CRC calculation 0 LSB first Initial value 1 MSB first 0 CRCAEN This bit is used to enable the automatic CRC calculation mode If entering the HALT HALT H mode when the CRCAEN bit is 1 the CRC calc...

Page 624: ...bits with the interrupt generated when the automatic CRC calculation is completed 19 3 1 Manual CRC Calculation Mode In the manual CRC calculation mode the calculation result is output to the CRC calc...

Page 625: ...sing Flow 1 Serial Transmission LSB First Write the initial value to the CRCRES register CRCRES 0xFFFF Start Write transmit data to the CRCDATA register CRCDATA 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28...

Page 626: ...culation result is added to the last two bytes Figure 19 4 CRC Calculation Processing Flow 2 Serial Reception LSB First Write the initial value to the CRCRES register CRCRES 0xFFFF Start Write receive...

Page 627: ...sion MSB First Write the initial value to the CRCRES register CRCRES 0xFFFF Start Write transmit data to the CRCDATA register CRCDATA 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x81 0x7F End When CR...

Page 628: ...culation result is added to the last two bytes Figure 19 6 CRC Calculation Processing Flow 4 Serial Reception MSB First Write the initial value to the CRCRES register CRCRES 0xFFFF Start Write receive...

Page 629: ...e CRCDATA register the calculation result is stored in the CRCRES register on the next clock rising edge The CRC calculation result can be checked anytime by reading the CRCRES register Figure 19 7 sh...

Page 630: ...Set CRC calculation start address Set CRC calculation start segment Set CRC calculation end address Set CRC calculation end segment Set the values of address and segment in which the CRC calculation...

Page 631: ...he MCU status interrupt is generated Enable disable the automatic CRC calculation completion interrupt is set by the MCU status interrupt enable register MCINTEL See Chapter 29 Safety Function for det...

Page 632: ...Chapter 20 Analog Comparator...

Page 633: ...t to the two pins Compare a voltage input to the one pin with the internal reference voltage Approx 0 8V Table 20 1 shows the number of channels Table 20 1 Number of Analog Comparator channels Channel...

Page 634: ...ated by the voltage comparison are available Rising edge of the comparison result Falling edge of the comparison result Rising edge and Falling edeg of the comparison result The sampling with a clock...

Page 635: ...MOD Comparator n mode register CMPnD Analog Comparator n Output CMP0D can be used as a trigger even source for the Functional Timer CMPnINT Analog Comparator n Interrupt Figure 20 1 Configuration of A...

Page 636: ...Pin name Shared port Setting Register Setting value ML62Q1300 group ML62Q1500 ML62Q1700 group 16pin product 20pin product 24pin product 32pin product 48pin product 52pin product 64pin product 80pin pr...

Page 637: ...d 0xF840 Comparator 0 control register CMP0CON R W 8 0x00 0xF841 Reserved R 8 0x00 0xF842 Comparator 0 mode register CMP0MODL CMP0MOD R W 8 16 0x00 0xF843 CMP0MODH R W 8 0x00 0xF844 to 0xF847 Reserved...

Page 638: ...ate the comparison result of the analog comparator The last comparison result is retained when the comparator is stopped 0 CMPnP CMPnM or 0 8V internal reference Initial 1 CMPnP CMPnM or 0 8V internal...

Page 639: ...og comparator 0 Use a reference voltage input from the CMPnM pin initial value 1 Uses the internal 0 8V reference voltage 7 Reserved bit 6 to 4 CMPnDIV2 to CMPnDIV0 These bits are used to choose frequ...

Page 640: ...K is chosen and ENOSC bit of FCON register is 0 the sampling function is not available When the HSCLK is chosen for the sampling block and the high speed clock is not oscillating the sampling circuit...

Page 641: ...e clock supply using the block clock control register 3 BCKCON3 Release the analog comparator reset using the block reset control register 3 BRECON3 2 Choose the interrupt mode and sampling conditions...

Page 642: ...ling when the falling edge rising edge both edge interrupt mode is chosen Figure 20 5 shows the interrupt generation timing with sampling when the rising edge interrupt mode is chosen Figure 20 6 show...

Page 643: ...pt Mode is chosen Figure 20 6 Analog Comparator Interrupt Generation Timing in STOP STOP D Mode When Falling edge Interrupt Mode is chosen System clock Comparison result display bit CMPnD Interrupt CM...

Page 644: ...Chapter 21 D A Converter...

Page 645: ...signals to analog signals The number of D A converter channels is dependent of the product specification Table 21 1 shows the number of channels Table 21 1 Number of D A converter channels Channel no...

Page 646: ...s Manual Chapter 21 D A Converter FEUL62Q1000 21 2 21 1 1 Features 8 bit resolution R 2R ladder method Analog output voltage DACOUT0 DACOUT1 Output voltage VDD x Setting value in the SFR 256 Output im...

Page 647: ...CON D A converter 0 control register DACCODE D A converter 0 code register DACCON1 D A converter 1 control register DACCODE1 D A converter 1 code register Figure 21 1 Configuration of D A Converter Ci...

Page 648: ...register settings Pin name Shared port Setting Register Setting value Pin name ML62Q1300 group ML62Q1500 ML62Q1700 group 16pin product 20 pin product 24pin product 32pin product 48pin product 52pin p...

Page 649: ...tial Value Byte Word 0xF860 D A converter 0 control register DACCON R W 8 0x00 0xF861 Reserved R 8 0x00 0xF862 D A converter 0 code register DACCODE R W 8 0x00 0xF863 to 0xF867 Reserved R 8 0x00 0xF86...

Page 650: ...N R W R R R R R R R R R R R R R R R R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit symbol name Description 15 to 1 Reserved bit 0 DAEN This bit is used to enable or disable the operation...

Page 651: ...8bit Initial value 0x00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word Byte DACCODE Bit d7 d6 d5 d4 d3 d2 d1 d0 R W R R R R R R R R R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 652: ...EN1 R W R R R R R R R R R R R R R R R R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit symbol name Description 7 to 1 Reserved bit 0 DAEN1 This bit is used to enable or disable the operati...

Page 653: ...bit Initial value 0x00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word Byte DACCODE1 Bit d7 d6 d5 d4 d3 d2 d1 d0 R W R R R R R R R R R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 654: ...alue of the D A converter 1 Set the general purpose port assigned for DACOUTn pin to the primary function and high impedance DACOUT0 P01 P0MOD1 0x00 DACOUT1 P44 P4MOD4 0x00 Set DACCODEn register Set P...

Page 655: ...Chapter 22 Voltage Level Supervisor...

Page 656: ...ge Level Supervisor FEUL62Q1000 22 1 22 Voltage Level Supervisor 22 1 General Description ML62Q1000 series has the Voltage Level Supervisor VLS0 that detects whether the voltage level of VDD is lower...

Page 657: ...age level of VDD only once The interrupt occurs after detecting the voltage of VDD is lower than the threshold voltage indicates the MCU is in the low voltage condition Supervisor mode Detect continuo...

Page 658: ...S0 VLS0CON Voltage level supervisor 0 control register VLS0MOD Voltage level supervisor 0 mode register VLS0LV Voltage level supervisor 0 level register VLS0SMP Voltage level supervisor 0 sampling reg...

Page 659: ...yte Word 0xF850 Voltage level supervisor 0 control register VLS0CON R W 8 0x00 0xF851 Reserved R 8 0x00 0xF852 Voltage level supervisor 0 mode register VLS0MOD R W 8 0x00 0xF853 Reserved R 8 0x00 0xF8...

Page 660: ...itoring the voltage level retains the last detection result This bit is cleared to 0 by writing 1 to this bit but not cleared by writing 0 Also this bit is cleared to 0 when the VL0 stars operating 0...

Page 661: ...ects the voltage level of VDD only once When VLS0SEL 1 0 bits is 0x02 the interrupt occurs when detecting the voltage level of VDD The result can be checked by reading VLS0F bit of VLS0CON register 01...

Page 662: ...e only when the VLS0RF bit is 1 The VLS0 is running in the single mode The MCU is unable to enter the STOP STOP D mode Enter the STOP STOP D mode when the VLS0 is not running when the VLS0EN bit is 0...

Page 663: ...0 Word Byte VLS0LV Bit VLS0L V3 VLS0L V2 VLS0L V1 VLS0L V0 R W R R R R R R R R R R R R R W R W R W R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit symbol name Description 7 to 4 Reserved...

Page 664: ...DI V1 VLS0DI V0 VLS0S M1 VLS0S M0 R W R R R R R R R R R R W R W R W R W R W R R Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit symbol name Description 7 Reserved bit 6 to 4 VLS0DIV2 to VLS0D...

Page 665: ...through the VLS0RF flag as at the time the detection result becomes valid The detection still continues By enabling generation of the VLS0 interrupt or VLS0 reset the power supply voltage can be const...

Page 666: ...in the supervisor mode Figure 22 2 Flow chart for starting the VLS in the supervisor mode Specify VLS0LV3 to VLS0LV0 bits of VLS0LV register Start Reset release Write 0x02 or 0x03 to VLS0AMD 1 0 of V...

Page 667: ...er 5 Set the VLS0EN bit of the VLS0CON register to 1 VLS0 starts operation in the supervisor mode 6 After approximately 300 s approx 300 s sampling clock cycle x 3 when sampling is enabled passed the...

Page 668: ...result of the VLS0 comparator is below the threshold voltage VVLSF and this condition continues for the duration of three cycles or more of the sampling clock the VLS0F bit is set to 1 and the VLS0 r...

Page 669: ...0x03 to VLS0AMD 1 0 bits of VLS0MOD register in order to choose the supervisor mode 4 Choose an operation function by the VLS0SEL1 and VLS0SEL0 bits of the VLS0MOD register 5 Write 1 to the VLS0EN bit...

Page 670: ...e sampling clock 9 If the comparison result of the VLS0 comparator is below the threshold voltage VVLSF and this condition continues for the duration of three cycles or more of the sampling clock the...

Page 671: ...ode Figure 22 7 Flow chart for starting the VLS in the single mode Specify VLS0LV3 VLS0LV0 bits of VLS0LV register Start Reset release Write 0x00 or 0x01 to VLS0AMD 1 0 of VLS0MOD register 0x00 Single...

Page 672: ...single mode 1 4 Choose an operation function by the VLS0SEL1 and VLS0SEL0 bits of the VLS0MOD register 5 Write 1 to the VLS0EN bit to enable VLS0 operation 6 If VDD is below the threshold voltage VVLS...

Page 673: ...5 Write 1 to the VLS0EN bit to enable VLS0 operation 6 Wait until the comparison result of the VLS0 comparator is stabilized 7 If VDD is below the threshold voltage VVLSF after three cycles of the sam...

Page 674: ...VLS0AMD 1 0 bits of VLS0MOD register in order to choose the single mode 2 4 Choose an operation function by the VLS0SEL1 and VLS0SEL0 bits of the VLS0MOD register 5 Write 1 to the VLS0EN bit to enable...

Page 675: ...nable VLS0 operation 6 Wait until the comparison result of the VLS0 comparator is stabilized 7 If VDD is below the threshold voltage VVLSF after three cycles of the sampling clock the VLS0F bit is set...

Page 676: ...Chapter 23 Successive Approximation Type A D Converter...

Page 677: ...onverts an analog input level to a digital value The number of A D Converter channels is dependent of the product specification Table 23 1 shows the number of channels Table 23 1 Number of A D Convert...

Page 678: ...on for target channels Consecutive scan conversion with a specific interval time One conversion result register for each channel Upper Lower limit is configurable for the conversion result generates a...

Page 679: ...ster SADLOL SA ADC lower limit setting register SADULSn SA ADC upper lower limit status registern n n 0 1 VREFCON reference voltage control register SADTMOD SA ADC test mode register SADINT SA ADC int...

Page 680: ...pproximation type A D converter I O 1 AIN2 I Successive approximation type A D converter I O 2 AIN3 I Successive approximation type A D converter I O 3 AIN4 I Successive approximation type A D convert...

Page 681: ...N4 P24 8 th Func P2MOD4 0111_0000 5 AIN5 P25 8 th Func P2MOD5 0111_0000 6 AIN6 P26 8 th Func P2MOD6 0111_0000 7 AIN7 P27 8 th Func P2MOD7 0111_0000 8 AIN8 P65 8 th Func P6MOD5 0111_0000 9 AIN9 P66 8 t...

Page 682: ...0x00 0xF810 SA ADC result register 8 SADR8L SADR8 R 8 16 0x00 0xF811 SADR8H R 8 0x00 0xF812 SA ADC result register 9 SADR9L SADR9 R 8 16 0x00 0xF813 SADR9H R 8 0x00 0xF814 SA ADC result register 10 S...

Page 683: ...setting register SADSTML SADSTM R W 8 16 0x00 0xF833 SADSTMH R W 8 0x00 0xF834 SA ADC upper lower limit mode register SADLMODL SADLMOD R W 8 16 0x00 0xF835 SADLMODH R W 8 0x00 0xF836 SA ADC upper lim...

Page 684: ...hannel 11 AIN11 SADR12 The conversion result of channel 12 AIN12 SADR13 The conversion result of channel 13 AIN13 SADR14 The conversion result of channel 14 AIN14 SADR15 The conversion result of chann...

Page 685: ...er The result of each channel is overwritten Use this register when transfering conversion results on multiple channels to RAM using the DMA controller The A D conversion test result on channel 17 is...

Page 686: ...imit on channel 1 AIN1 SAULS02 Detection result for the upper lower limit on channel 2 AIN2 SAULS03 Detection result for the upper lower limit on channel 3 AIN3 SAULS04 Detection result for the upper...

Page 687: ...s are cleared or the LSI gets the system reset When using the A D conversion result upper lower limit detection function SALEN 1 the interrupt request is generated at the same time the corresponding b...

Page 688: ...ion When this bit is set to 1 the sample hold capacitance is discharged to Vss level 0 Start the A D conversion without discharging the electrical charge accumulated in the sample hold capacitor Initi...

Page 689: ...the trigger operation 0 SARUN This bit is used to start or stop the A D conversion Write 1 to this bit to start the A D conversion and 0 to stop it When 0 is written to SALP bit and the A D conversion...

Page 690: ...l 1 SACH02 Enable or Disable the A D conversion on channel 2 SACH03 Enable or Disable the A D conversion on channel 3 SACH04 Enable or Disable the A D conversion on channel 4 SACH05 Enable or Disable...

Page 691: ...are used to choose channel n n 16 17 of the A D converter and enable disable the conversion SACH16 Enable or Disable the A D conversion on channel 16 Temperature sensor SACH17 Enable or Disable the A...

Page 692: ...nel 5 are A D converted consecutively and before the A D conversion of channel 2 is started The next A D conversion starts at the timing that the value set in this register has been counted with the A...

Page 693: ...egisters 0 and 1 SADULS0 and SADULS1 get to 1 and generates the SA ADC interrupt request 00 SADLOL value A D conversion value SADUPL value initial value 01 A D conversion value SADUPL value 10 A D con...

Page 694: ...H SADUPLL Bit d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 R W R W R W R W R W R W R W R W R W R W R W R R R R R R Initial value 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 SA ADC Lower Limit Setting Register SADLOL 23 2...

Page 695: ...ved bit 0 VREFEN This bit is used to enable the operation of internal reference voltage and the temperature sensor When using the internal reference voltage approx 1 55V or temperature sensor set the...

Page 696: ...W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit symbol name Description 7 to 1 Reserved bit 0 SADIMD This bit is used to choose the occurrence timing of SA ADC interrupt request 0 Make the...

Page 697: ...0 0 0 0 0 Bit No Bit symbol name Description 7 to 5 Reserved bit 4 to 0 SASTS4 to SASTS0 These bits are used to choose the source of the trigger event for SA ADC 00000 16 bit Timer 0 interrupt TM0INT...

Page 698: ...he A D conversion result is stored in the SA ADC result register SADR Address 0xF0BA SADTMOD Access R W Access size 8bit Initial value 0x00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word Byte SADTMOD Bit...

Page 699: ...version is started Setting start Set the general purpose port of AINn to the both input and output are disable To use the voltage that is input from the VREF pin as the reference voltage set the mode...

Page 700: ...re disable To use the voltage that is input from the VREF pin as the reference voltage set the mode of that disables the input and disables the output End If enabling SADINT SA ADC interrupt set the E...

Page 701: ...th input and output are disable To use the voltage that is input from the VREF pin as the reference voltage set the mode of that disables the input and disables the output End If enabling SADINT SA AD...

Page 702: ...Presence absence of discharge can be chosen by SAINIT bit of SADMOD register It takes two clocks of SAD_CLK for discharging The sampling time can be chosen by SASHT1 and SASHT0 bits of the SADMOD reg...

Page 703: ...ng the SADTMOD register SADTMOD 0x02 6 A D convert the AINn pin conversion result 3 7 A D convert AIN internal reference voltage approx 1 55V by setting the SADTMOD register SADTMOD 0x03 8 A D convert...

Page 704: ...nce voltage Table 23 3 A D Conversion time when using VDD or VREF pin as reference voltage SADMOD Conversion clock count Conversion time SAD_CLK SASHT 3 0 32kHz 0 5MHz 1MHz 2MHz 4MHz 8MHz 0 0 0 0 14 4...

Page 705: ...harge to the VSS level at the start of A D conversion the A D conversion time shown in Table 23 3 and 23 4 is increased by two clocks of the conversion clock SAD_CLK The A D conversion time does not i...

Page 706: ...nt Sampling time SAD_CLK SASHT 3 0 32kHz 0 5MHz 1MHz 2MHz 4MHz 8MHz 0 0 0 0 1 30 s Prohibited Prohibited Prohibited Prohibited Prohibited 0 0 0 1 2 Prohibited 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0...

Page 707: ...es If the sampling time above is unsatisfied connect the external capacitor to satisfy the following formula External capacitor 1 2 Sampling time 8 2 n Resolution of A D converter C1 External capacito...

Page 708: ...se reduction Perform A D conversion in the HALT mode Do not have clock input output to and from a pin located in the vicinity of the pin in which A D conversion is in progress Do not have clock input...

Page 709: ...Chapter 24 Regulator...

Page 710: ...logic voltage VDDL independent of the variation of VDD 1 6 V to 5 5 V using an amplifier for the low power consumption The VDDL generated by the regulator is supplied to peripheral circuits such as th...

Page 711: ...ser s Manual Chapter 24 Regulator FEUL62Q1000 24 2 24 1 1 Features Mode VDDL voltage STOP mode 1 55 V HALT mode 1 55 V HALT H mode 1 55 V Program run mode 1 55 V STOP D mode content of RAM and SFR can...

Page 712: ...24 1 2 Configuration Figure 24 2 shows the configuration of the internal power supply Figure 24 2 Internal Power Supply Configuration VDD VSS VDD 1 6 V to 5 5 V VDDL Regulator Logic circuit CL 1 F Fl...

Page 713: ...to use for an external device voltage 24 2 Description of Operation After power on VDDL becomes approximately 1 55 V In the STOP D mode VDDL is lowered to approximately 1 1 V to reduce the standby cu...

Page 714: ...Chapter 25 Flash Memory...

Page 715: ...emory Programming method Tool Register Communication Reference Chapter Programming by the on chip debug function On chip debug emulator EASE1000 or other flash programmers Chapter 28 On chip Debug fun...

Page 716: ...0x1F 0x0FFF ML62Q1531 1541 1551 48K byte 0x0 0x0000 to 0x0 0xBFFF ML62Q1532 1542 1552 64K byte 0x0 0x0000 to 0x0 0xFFFF ML62Q1533 1543 1553 1563 1573 96K byte 0x0 0x0000 to 0x1 0x7FFF ML62Q1534 1544...

Page 717: ...e 16K byte ML62Q1300 group 2K byte ML62Q1500 group 4K byte ML62Q1700 group 4K byte Sector erase 1K byte 128 byte Programming 4 byte 32bit 1 byte 8bit Erasing and programming time Chip erase ISP only M...

Page 718: ...5 4 25 1 1 List of Pins Programming by the ISP function uses the following pins Signal name I O Function RESET_N I Input signal for entering the ISP mode TEST0 I O Input signal for entering the ISP mo...

Page 719: ...LASHD0L FLASHD0 R W 8 16 0xFF 0xF093 FLASHD0H R W 8 0xFF 0xF094 Flash data register 1 FLASHD1L FLASHD1 R W 8 16 0xFF 0xF095 FLASHD1H R W 8 0xFF 0xF096 Flash control register FLASHCON W 8 0x00 0xF097 R...

Page 720: ...7 6 5 4 3 2 1 0 Word FLASHA Byte FLASHAH FLASHAL Bit FA15 FA14 FA13 FA12 FA11 FA10 FA9 FA8 FA7 FA6 FA5 FA4 FA3 FA2 FA1 FA0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Initial...

Page 721: ...Q1300 group Segment 0 Block 0 0x0000 to 0x3FFF 16K byte 0x00 0x0000 Block 1 0x4000 to 0x7FFF 16K byte 0x4000 Block 2 0x8000 to 0xBFFF 16K byte 0x8000 Block 3 0xC000 to 0xFFFF 16K byte 0xC000 Segment 3...

Page 722: ...tor 1 0x0400 to 0x07FF 1K byte 0x0400 Sector 62 0xF800 to 0xFBFF 1K byte 0xF800 Sector 63 0xFC00 to 0xFFFF 1K byte 0xFC00 Segment 1 Sector 64 0x0000 to 0x03FF 1K byte 0x01 0x0000 Sector 65 0x0400 to 0...

Page 723: ...ming target Register Description Note Program memory space Four bytes specified in FLASHD0 register FLASHD0H FLASHD0L and FLASHD1 register FLASHD1H FLASHD1L The programming starts by writing data into...

Page 724: ...data There are some differences for programming the program memory space and the data flash area Programming target Register Description Note Program memory space Four bytes specified in FLASHD0 regis...

Page 725: ...0x00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word Byte FLASHCON Bit FSERS FERS R W R R R R R R R R R R R R R R W W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit symbol name Description 15 to...

Page 726: ...scription 15 to 8 Reserved bit 7 to 0 fac7 to fac0 These bits are used to accept for erasing programming the flash memory in order to prevent an unintended erasing programming operation When 0FAH and...

Page 727: ...Access size 8bit Initial value 0x00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word Byte FLASHSLF Bit FSELF R W R R R R R R R R R R R R R R R R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit s...

Page 728: ...sing 0 Data flash memory is not in the state of erasing Initial value 1 Data flash memory is in the state of erasing FLASHSTA is used when erasing or programming the data flash memory Erasing Programm...

Page 729: ...LASHACP incorporated 1 Flash memory erase program Supported only when system clock is HSCLK 2 Note on user program programming Before programming the user program prepare a program for self programmin...

Page 730: ...imum 50 ms whereas peripheral circuits continue operation Therefore clear the WDT counter accordingly For block sector erase place two NOP instructions following the instruction used to set FERS FSERS...

Page 731: ...rdingly For data programming setting place two NOP instructions following the instruction used to set the programming data in the FLASHD1 register FSELF 1 Start programming FLASHACP 0xFA FLASHACP 0xF5...

Page 732: ...instructions following the instruction used to set FERS FSERS bits of the FLASHCON register to 1 FSELF 1 Start data flash erase FLASHACP 0xFA FLASHACP 0xF5 End FLASHSEG 0x1F FLASHAR Address to be eras...

Page 733: ...Address to be erased Enable programming flash Flash acceptor setting Flash address setting Set the high speed clock for the system clock through the FCON register If using interrupts execute MCINTEL...

Page 734: ...ock Generation Circuit for enabling the high speed clock oscillation and switching the system clock If power outage or forced termination due to a reset occurs Data in flash memory is not guaranteed P...

Page 735: ...ble 25 6 describes the communication method of the ISP function Table 25 6 ISP Function Communication Method Item Description Pins used for ISP function RESET_N and TEST0 pins Pins used when entering...

Page 736: ...on completion confirmation 1 0x01 read 0xC0 or 0x80 read 0x05 Command transmission completion confirmation 2 0x91 read 0x00 read 0x00 Common setting Segment value setting 0xC6 0x00 0x1F segment value...

Page 737: ...pin D Transmit data 0x80 using the UART communication baud rate configured in the host side E Transmit data using the UART communication baud rate configured in the host side in the following order 0...

Page 738: ...Erasing Programming Flash Memory Overview Start ISP End Initial setting Erase specified flash memory area Verify specified flash memory area See Section 25 4 5 1 Initial Setting for details See Sectio...

Page 739: ...on completion confirmation 1 Initial setting command transmission 2 Command transmission completion confirmation 2 0 has been read in the 2 nd byte YES NO Flash erase program and verify NO YES After c...

Page 740: ...t and address Block chip erase command BUSY signal confirmation 3 rd byte is 0x00 YES NO End If the 3 rd byte of BUSY signal confirmation command is other than 0x00 it indicates the erase or write is...

Page 741: ...d BUSY signal confirmation 3 rd byte is 0x00 YES NO End Setting for segment and address Code area programming data setting lower 2 bytes Code area programming data setting higher 2 bytes Write complet...

Page 742: ...nd Confirm collation result of expected values End Setting for segment and address Code area programming data setting lower 2 bytes Code area programming data setting higher 2 bytes Verify completed f...

Page 743: ...Chapter 26 Code Option...

Page 744: ...ption area can be erased or programmed through the on chip debug function self rewrite function of flash memory or ISP function Figure 26 1 Code Option Overview 26 1 1 Function List The following choi...

Page 745: ...3 2 Unused ROM Area Access Reset Function for the unused ROM area access reset 0 Unused ROM area access reset disabled 1 Unused ROM area access reset enabled initial value 11 to 9 Reserved bits 8 REM...

Page 746: ...tion 15 to 4 Reserved bits 3 2 PLLMD1 PLLMD0 These bits are used to choose the PLL reference frequency 00 Do not use 01 Do not use 10 PLL reference frequency 24 MHz 11 PLL reference frequency 16 MHz i...

Page 747: ...f CREA15 to 12 bits and CRES1 to 0 bits For details on REMAPADD see Section 2 7 3 Flash Remap Address Register REMAPADD The MCU remaps to the address specified with the CREA15 to 12 bits and the CRES1...

Page 748: ...x0 BFD2 0x0 BFD0 ML62Q1532 1542 1552 64K byte 0x0 FFC0 to 0x0 FFFF 0x0 FFD4 0x0 FFD2 0x0 FFD0 ML62Q1533 1543 1553 1563 1573 96K byte 0x1 7FC0 to 0x1 7FFF 0x1 7FD4 0x1 7FD2 0x1 7FD0 ML62Q1534 1544 1554...

Page 749: ...0ffffh 0ffc0h dw 0ffffh 0ffc2h dw 0ffffh 0ffc4h dw 0ffffh 0ffc6h dw 0ffffh 0ffc8h dw 0ffffh 0ffcah dw 0ffffh 0ffcch dw 0ffffh 0ffceh dw 0eef8h 0ffd0h CODEOP0 Unused ROM area access reset disabled rem...

Page 750: ...Chapter 27 LCD Driver...

Page 751: ...2Q1747 60seg 8com com Max 65seg 3com seg Max Unused segment common output pins can be used as general purpose input output pins 1 1 duty to 1 8 duty 1 3 bias bias generation circuit embedded LCD drive...

Page 752: ...SEG0 pin to SEG4 pin are shared with common output pins or general purpose input output pins SEG5 pin to SEG64 pin are shared with general purpose input output pins BIASCON Bias control register DSPMO...

Page 753: ...te VL2 and VL1 by the means of capacitance voltage division using the capacitor C12 4 External supply type Supply voltages to VL1 to VL3 externally Setting the BSON bit of the bias circuit control reg...

Page 754: ...viding circuit OFF VL2 VL1 VSS VDD Voltage regulator circuit OFF C L3 C L2 C L1 VL3 C2 C1 To LCD driver VL1 to VL3 4 External supply type OFF LCD control Block Boosting dividing circuit ON VL2 VL1 VSS...

Page 755: ...ment output pin P10 COM4 SEG1 General purpose input output pin Common output pin Segment output pin P11 COM5 SEG2 General purpose input output pin Common output pin Segment output pin P12 COM6 SEG3 Ge...

Page 756: ...Segment output pin P21 SEG27 General purpose input output pin Segment output pin P22 SEG28 General purpose input output pin Segment output pin P23 SEG29 General purpose input output pin Segment output...

Page 757: ...pose input output pin Segment output pin P32 SEG51 General purpose input output pin Segment output pin P33 SEG52 General purpose input output pin Segment output pin P60 SEG53 General purpose input out...

Page 758: ...x00 0xF0F5 DSPCONH R W 8 0x00 0xF0F6 Segment mode register 0 SEGMOD0L SEGMOD0 R W 8 16 0x00 0xF0F7 SEGMOD0H R W 8 0x00 0xF0F8 Segment mode register 1 SEGMOD1L SEGMOD1 R W 8 16 0x00 0xF0F9 SEGMOD1H R W...

Page 759: ...CN4 to LCN0 These bits are used to adjust the display contrast in 32 voltage levels It is adjustable by controlling the VL1 voltage See the electrical characteristics in the data sheet for more detail...

Page 760: ...000 27 10 111 1 128 LSCLK 256Hz 0 BSON This bit is used to control the bias generation circuit operation Setting the BSON bit to 1 generates the LCD driving voltages VL1 to VL3 0 Bias generation circu...

Page 761: ...bits are used to select the frame frequency of the LCD driver 000 Frame frequency 32 Hz 001 Frame frequency 38 Hz 010 Frame frequency 64 Hz initial value 011 Frame frequency 75 Hz 100 Frame frequency...

Page 762: ...to 61 initial value 001 Display 2 Display the higher 4 bit data of the display register DSPR00 to 61 010 Switching display 1 Display the data area in the display 1 and display 2 alternately every one...

Page 763: ...ial value 1 SEG13 12 S12MD This bit is used to select the general purpose input output and segment output functions 0 P93 Initial value 1 SEG12 11 S11MD This bit is used to select the general purpose...

Page 764: ...and segment output functions 0 P11 Initial value 1 SEG2 1 S1MD This bit is used to select the general purpose input output and segment output functions 0 P10 Initial value 1 SEG1 0 S0MD This bit is u...

Page 765: ...Initial value 1 SEG29 12 S28MD This bit is used to select the general purpose input output and segment output functions 0 P22 Initial value 1 SEG28 11 S27MD This bit is used to select the general purp...

Page 766: ...and segment output functions 0 PA1 Initial value 1 SEG18 1 S17MD This bit is used to select the general purpose input output and segment output functions 0 PA0 Initial value 1 SEG17 0 S16MD This bit i...

Page 767: ...Initial value 1 SEG45 12 S44MD This bit is used to select the general purpose input output and segment output functions 0 PB3 Initial value 1 SEG44 11 S43MD This bit is used to select the general purp...

Page 768: ...and segment output functions 0 P56 Initial value 1 SEG34 1 S33MD This bit is used to select the general purpose input output and segment output functions 0 P27 Initial value 1 SEG33 0 S32MD This bit i...

Page 769: ...Initial value 1 SEG61 12 S60MD This bit is used to select the general purpose input output and segment output functions 0 P67 Initial value 1 SEG60 11 S59MD This bit is used to select the general purp...

Page 770: ...and segment output functions 0 P31 Initial value 1 SEG50 1 S49MD This bit is used to select the general purpose input output and segment output functions 0 P30 Initial value 1 SEG49 0 S48MD This bit i...

Page 771: ...8 7 6 5 4 3 2 1 0 Word SEGMOD4 Byte SEGMOD4L But S64M D R W R R R R R R R R R R R R R R R R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit name Description 15 to 1 Reserved bits 0 S64MD T...

Page 772: ...125 DSPR37 0xF126 DSPRW38 DSPR38 0xF127 DSPR39 0xF128 DSPRW40 DSPR40 0xF129 DSPR41 0xF12A DSPRW42 DSPR42 0xF12B DSPR43 0xF12C DSPRW44 DSPR44 0xF12D DSPR45 0xF12E DSPRW46 DSPR46 0xF12F DSPR47 0xF130 DS...

Page 773: ...7 ML62Q1743 ML62Q1744 ML62Q1745 ML62Q1746 ML62Q1747 DSPR00 0xF100 SEG0 DSPR01 0xF101 SEG1 DSPR02 0xF102 SEG2 DSPR03 0xF103 SEG3 DSPR04 0xF104 SEG4 DSPR05 0xF105 SEG5 DSPR06 0xF106 SEG6 DSPR07 0xF107 S...

Page 774: ...735 ML62Q1736 ML62Q1737 ML62Q1743 ML62Q1744 ML62Q1745 ML62Q1746 ML62Q1747 DSPR39 0xF127 SEG39 DSPR40 0xF128 SEG40 DSPR41 0xF129 SEG41 DSPR42 0xF12A SEG42 DSPR43 0xF12B SEG43 DSPR44 0xF12C SEG44 DSPR45...

Page 775: ...bit of the bias control register BIASCON to 1 Set display data in the display registers DSPR00 to DSPR64 Wait for the bias activation time tBIAS or longer Then set to the display mode using the LMD1...

Page 776: ...mode Figure 27 5 Waveform A Output from Common Pins in 1 3 Duty Figure 27 6 shows the waveform A output from the common pins in 1 4 duty mode Figure 27 6 Waveform A Output from Common Pins in 1 4 Duty...

Page 777: ...orm B Output from Common Pins in 1 3 Duty Figure 27 8 shows the waveform B output from the common pins in 1 4 duty mode Figure 27 8 Waveform B Output from Common Pins in 1 4 Duty 0 COM0 VL3 VL2 VL1 VS...

Page 778: ...egment pins in 1 3 duty mode Figure 27 9 Waveform A Output from Segment Pins in 1 3 Duty 0 SEGn VL3 VL2 VL1 VSS Frame 1 2 Data 0 0 0 SEGn VL3 VL2 VL1 VSS Data 1 0 0 SEGn VL3 VL2 VL1 VSS Data 0 1 0 SEG...

Page 779: ...Waveform A Output from Segment Pins in 1 4 Duty 0 SEGn VL3 VL2 VL1 VSS Frame 1 2 3 Data 0 0 0 0 SEGn VL3 VL2 VL1 VSS Data 1 0 0 0 SEGn VL3 VL2 VL1 VSS Data 1 1 0 0 SEGn VL3 VL2 VL1 VSS Data 0 1 0 1 S...

Page 780: ...1 Waveform B Output from Segment Pins in 1 3 Duty 0 SEGn VL3 VL2 VL1 VSS Frame 1 2 Data 0 0 0 SEGn VL3 VL2 VL1 VSS Data 1 0 0 SEGn VL3 VL2 VL1 VSS Data 0 1 0 SEGn VL3 VL2 VL1 VSS Data 1 1 0 SEGn VL3 V...

Page 781: ...in 1 4 Duty 0 SEGn VL3 VL2 VL1 VSS Frame Data 0 0 0 0 SEGn VL3 VL2 VL1 VSS Data SEGn VL3 VL2 VL1 VSS Data SEGn VL3 VL2 VL1 VSS Data SEGn VL3 VL2 VL1 VSS Data SEGn VL3 VL2 VL1 VSS Data SEGn VL3 VL2 VL...

Page 782: ...and LED drive mode Figure 27 13 Waveform A Output from Common Pins in 1 3 Duty and LED drive mode Figure 27 14 shows the waveform A output from the common pins in 1 4 duty and LED drive mode Figure 2...

Page 783: ...15 Waveform B Output from Common Pins in 1 3 Duty and LED drive mode Figure 27 16 shows the waveform B output from the common pins in 1 4 duty and LED drive mode Figure 27 16 Waveform B Output from C...

Page 784: ...output from the segment pins in 1 3 duty and LED drive mode Figure 27 17 Waveform A Output from Segment Pins in 1 3 Duty and LED drive mode 1 0 1 0 SEGn VL3 VSS Frame 1 2 Data 0 0 0 SEGn VL3 VSS Data...

Page 785: ...d LED drive mode Figure 27 18 Waveform A Output from Segment Pins in 1 4 Duty and LED drive mode 0 SEGn VL3 VSS Frame 1 2 3 Data 0 0 0 0 SEGn VL3 VSS Data 1 0 0 0 SEGn VL3 VSS Data 1 1 0 0 SEGn VL3 VS...

Page 786: ...ED drive mode Figure 27 19 Waveform B Output from Segment Pins in 1 3 Duty and LED drive mode 0 1 0 SEGn VL3 VSS Frame 1 2 Data 0 0 0 SEGn VL3 VSS Data 0 SEGn VL3 VSS Data 0 1 0 SEGn VL3 VSS Data 1 1...

Page 787: ...rm B Output from Segment Pins in 1 4 Duty and LED drive mode 0 SEGn VL3 VSS Frame Data 0 0 0 0 SEGn VL3 VSS Data SEGn VL3 VSS Data SEGn VL3 VSS Data SEGn VL3 VSS Data SEGn VL3 VSS Data SEGn VL3 VSS Da...

Page 788: ...Chapter 28 On Chip Debug Function...

Page 789: ...Description This function is used by connecting the host PC and LSI through the on chip debug emulator EASE1000 hereafter referred to as EASE1000 manufactured by LAPIS Semiconductor On board debugging...

Page 790: ...play change Register display change in the CPU Program download Program download read erase to from flash memory Data write read erase to from data flash Peripheral circuit operation continue stop con...

Page 791: ...3 VOUT power supply 3 3 V 100 mA of EASE1000 Figure 28 1 Connection Example When Using EASE1000 3 3 VOUT Power Supply 28 1 2 2 Using Power Supply of Target System VDD 1 6 V to 5 5 V Figure 28 2 shows...

Page 792: ...On Chip Debug Function FEUL62Q1000 28 4 28 1 3 List of Pins The following pins are used for the on chip debug function Signal name I O Function RESET_N I On chip debug function signal input P00 TEST0...

Page 793: ...s connected the current consumption increases as the on chip debug circuit inside the LSI works for the communication When using the 3 3 VOUT power supply of EASE1000 do not apply power of the target...

Page 794: ...ipheral operation continues during the break If the item checked off operation of the peripheral stops during the break Note The simplified RTC functions LTBRR register and TBCOUT1 output stop during...

Page 795: ...Chapter 29 Safety Function...

Page 796: ...fety Function FEUL62Q1000 29 1 29 Safety Function 29 1 General Description ML62Q1000 series has the safety functions to make a safe stop in case a failure is detected by executing the self diagnosis s...

Page 797: ...code option with reset status flag Clock mutual monitoring Monitor to check whether the oscillation of the high speed and low speed clocks are normal Available CRC calculation Detect data error in th...

Page 798: ...B6 SFR Guard Setting Register 1 SFRGD1L SFRGD1 R W 8 16 0x00 0xF0B7 SFRGD1H R W 8 0x00 0xF0B8 Reserved R 8 0x00 0xF0B9 Reserved R 8 0x00 0xF0BB Reserved R 8 0x00 0xF0BC RAM Parity Setting Register RAS...

Page 799: ...0 0 0 Bit No Bit symbol name Description 7 to 3 Reserved bit 2 to 0 RGD2 to RGD0 These bits are used to choose a protect area for writing on the RAM 000 All RAM area writable and readable Initial val...

Page 800: ...SFR is unwritable and readable 4 SGD04 This bit is used to disable BCKCONn register and BRECONn register n 0 to 3 See Chapter 4 Power management for details of the registers 0 The SFR is writable and...

Page 801: ...dable Initial value 1 The SFR is unwritable and readable 10 SGD1A This bit is used to disable SFRs related to the port A described in Chapter 17 General Purpose Port 0 The SFR is writable and readable...

Page 802: ...adable Initial value 1 The SFR is unwritable and readable 2 SGD12 This bit is used to disable SFRs related to the port 2 described in Chapter 17 General Purpose Port 0 The SFR is writable and readable...

Page 803: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word Byte RASFMOD Bit PERF PERE N R W R R R R R R R R R W R R R R R R R W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit symbol name Description 7 PERF Th...

Page 804: ...test for the communication function is disabled Initial value 1 The self test for the communication function is enabled 4 CMFT04 This bit is used to enable disable the self test for the serial commun...

Page 805: ...eserved bit 2 MCI2E This bit is used to enable disable the interrupt at the completion of data flash erasing programming 0 The data flash erasing programming completion interrupt is disabled Initial v...

Page 806: ...iption 7 to 3 Reserved bit 2 MCI2S This bit is used to indicate status of the data flash erasing programming completion interrupt 0 The data flash erasing programming completion interrupt has not been...

Page 807: ...W W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No Bit symbol name Description 15 MCIR This bit is a request bit for the MCU status interrupt Write 1 to this bit before returning from the interr...

Page 808: ...on test Figure 29 1 Communication Test Concept Diagram Figure 29 2 Communication Test Flow Chart Receive register HSCLK LSCLK RXDn SINn SCKn TXDn SOUTn Clock selection frequency division circuit Baud...

Page 809: ...0FFC0H to 0x7 0FFFFH ML62Q1576 ML62Q1566 ML62Q1556 0x2 0FFC0H to 0x7 0FFFFH ML62Q1575 ML62Q1565 ML62Q1555 0x2 07FC0H to 0x7 0FFFFH ML62Q1574 ML62Q1564 ML62Q1554 ML62Q1544 ML62Q1534 0x1 0FFC0H to 0x7 0...

Page 810: ...gh Speed Clock PLL Oscillation Circuit Oscillation Monitoring Example Figure 29 4 describes the setting for the monitoring example shown in Figure 29 3 Operation clock low speed clock FTnC Valid A 000...

Page 811: ...bits 0 Set the following items through the FTnTRG0 register of the functional timer n FTnST bit 1 Counter start through trigger event Enabled FTnSTC bit 1 Counter clear through trigger event for coun...

Page 812: ...Manual CRC calculation mode Performs calculation of arbitrary data written from the CPU or DMAC in units of 8 bits 29 3 5 WDT Counter Read The count value can be read from the watchdog timer counter r...

Page 813: ...Appendix A...

Page 814: ...xF014 Watchdog timer counter register L WDTMCL WDTMC R 8 16 0x00 0xF015 Watchdog timer counter register H WDTMCH R 8 0x00 0xF016 Watchdog timer status register WDTSTA R 8 0x01 0xF017 Reserved R 8 0x00...

Page 815: ...0xF043 ILC71 R W 8 0x00 0xF044 External Interrupt Control register 0L EICON0L EICON0 R W 8 16 0x00 0xF045 External Interrupt Control register 0H EICON0H R W 8 0x00 0xF046 Reserved R 8 0x00 0xF047 Res...

Page 816: ...gister 0 BRECON0L BRECON0 R W 8 16 0x00 0xF079 BRECON0H R W 8 0x00 0xF07A Block reset control register 1 BRECON1L BRECON1 R W 8 16 0x00 0xF07B BRECON1H R W 8 0x00 0xF07C Block reset control register 2...

Page 817: ...8 0x00 0xF0C4 Clock Backup Test Mode Acceptor FBTACP W 8 0x00 0xF0C5 Reserved R 8 0x00 0xF0C6 Clock Backup Test Mode register FBTCON R W 8 0x00 0xF0C7 Reserved R 8 0x00 0xF0C8 Simplified RTC Acceptor...

Page 818: ...8 16 0x40 0xF0F3 Display mode register H DSPMODH R W 8 0x00 0xF0F4 Display control register L DSPCONL DSPCON R W 8 16 0x00 0xF0F5 Display control register H DSPCONH R W 8 0x00 0xF0F6 Segment mode regi...

Page 819: ...0xF124 Display register 36 DSPR36 DSPRW36 R W 8 16 0xF125 Display register 37 DSPR37 R W 8 0xF126 Display register 38 DSPR38 DSPRW38 R W 8 16 0xF127 Display register 39 DSPR39 R W 8 0xF128 Display re...

Page 820: ...ort 1 mode register 01 P1MOD0 P1MOD01 R W 8 16 0x00 0xF213 P1MOD1 R W 8 0x00 0xF214 Port 1 mode register 23 P1MOD2 P1MOD23 R W 8 16 0x00 0xF215 P1MOD3 R W 8 0x00 0xF216 Port 1 mode register 45 P1MOD4...

Page 821: ...MOD01 R W 8 16 0x00 0xF243 P4MOD1 R W 8 0x00 0xF244 Port 4 mode register 23 P4MOD2 P4MOD23 R W 8 16 0x00 0xF245 P4MOD3 R W 8 0x00 0xF246 Port 4 mode register 45 P4MOD4 P4MOD45 R W 8 16 0x00 0xF247 P4M...

Page 822: ...8 0x00 0xF27F 0xF280 Port 8 data register P8DI P8D R W 8 16 0xFF 0xF281 P8DO R W 8 0x00 0xF282 Port 8 mode register 01 P8MOD0 P8MOD01 R W 8 16 0x00 0xF283 P8MOD1 R W 8 0x00 0xF284 Port 8 mode registe...

Page 823: ...F2 PORTXT mode register 01 PXTMOD0 PXTMOD01 R W 8 16 0x00 0xF2F3 PXTMOD1 R W 8 0x00 0xF2F4 to Reserved R 8 0x00 R 0xF2FF 0xF300 16 bit timer 0 data register L TMH0DL TMH0D R W 8 16 0xFF 0xF301 16 bit...

Page 824: ...6 bit timer 4 mode register H TMH4MODH R W 8 0x00 0xF32A 16 bit timer 5 mode register L TMH5MODL TMH5MOD R W 8 16 0x00 0xF32B 16 bit timer 5 mode register H TMH5MODH R W 8 0x00 0xF32C 16 bit timer 6 m...

Page 825: ...ter L TMHSTATL TMHSTAT R 8 16 0x00 0xF355 16 bit timer status register H TMHSTATH R 8 0x00 0xF356 to Reserved 0xF3FF 0xF400 FTM0 cycle register L FT0PL FT0P R W 8 16 0xFF 0xF401 FTM0 cycle register H...

Page 826: ...FT0DTL FT0DT R W 8 16 0x00 0xF431 FTM0 dead time register H FT0DTH R W 8 0x00 0xF432 FTM1 dead time register L FT1DTL FT1DT R W 8 16 0x00 0xF433 FTM1 dead time register H FT1DTH R W 8 0x00 0xF434 FTM2...

Page 827: ...0xF464 FTM2 mode register L FT2MODL FT2MOD R W 8 16 0x00 0xF465 FTM2 mode register H FT2MODH R W 8 0x40 0xF466 FTM3 mode register L FT3MODL FT3MOD R W 8 16 0x00 0xF467 FTM3 mode register H FT3MODH R W...

Page 828: ...R W 8 0x00 0xF494 FTM2 trigger register 1L FT2TRG1L FT2TRG1 R W 8 16 0x00 0xF495 FTM2 trigger register 1H FT2TRG1H R W 8 0x00 0xF496 FTM3 trigger register 1L FT3TRG1L FT3TRG1 R W 8 16 0x00 0xF497 FTM...

Page 829: ...W 8 16 0x00 0xF4C1 FTM0 interrupt clear register H FT0INTCH W 8 0x00 0xF4C2 FTM1 interrupt clear register L FT1INTCL FT1INTC W 8 16 0x00 0xF4C3 FTM1 interrupt clear register H FT1INTCH W 8 0x00 0xF4C4...

Page 830: ...612 UART00 status register UA00STAT R W 8 0x00 0xF613 Reserved R 8 0x00 0xF614 UART01 mode register L UA01MODL UA01MOD R W 8 16 0x00 0xF615 UART01 mode register H UA01MODH R W 8 0x00 0xF616 UART01 bau...

Page 831: ...nication unit 2 control register L SU2CONL SU2CON R W 8 16 0x00 0xF647 Serial communication unit 2 control register H SU2CONH R W 8 0x00 0xF648 Synchronous serial port 2 mode register L SIO2MODL SIO2M...

Page 832: ...xF676 UART31 baud rate register L UA31BRTL UA31BRT R W 8 16 0xFF 0xF677 UART31 baud rate register H UA31BRTH R W 8 0xFF 0xF678 UART31 baud rate adjustment register UA31BRC R W 8 0x00 0xF679 Reserved R...

Page 833: ...l port 5 mode register L SIO5MODL SIO5MOD R W 8 16 0x00 0xF6A9 Synchronous serial port 5 mode register H SIO5MODH R W 8 0x00 0xF6AA Synchronous serial port 5 status register SIO5STAT R W 8 0x00 0xF6AB...

Page 834: ...H slave I2US0ISR R W 8 0x00 0xF6DA to Reserved 0xF6E1 0xF6E2 I 2 C master 0 receive register I2M0RD R 8 0x00 0xF6E3 Reserved 0xF6E4 I 2 C master 0 slave address register I2M0SA R W 8 0x00 0xF6E5 Reser...

Page 835: ...A channel 1 transfer source address register L DC1SAL DC1SA R W 8 16 0x00 0xF70D DMA channel 1 transfer source address register H DC1SAH R W 8 0x00 0xF70E DMA channel 1 transfer destination address re...

Page 836: ...0x00 0xF825 SADULS0H R W 8 0x00 0xF826 SA ADC upper lower limit status register 1 SADULS1L SADULS1 R W 8 16 0x00 0xF827 SADULS1H R W 8 0x00 0xF828 SA ADC mode register SADMODL SADMOD R W 8 16 0x00 0xF...

Page 837: ...F 0xF850 Voltage level supervisor 0 control register VLS0CON R W 8 0x00 0xF851 Reserved R 8 0x00 0xF852 Voltage level supervisor 0 mode register VLS0MOD R W 8 0x00 0xF853 Reserved R 8 0x00 0xF854 Volt...

Page 838: ...te Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflo...

Page 839: ...ceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting contact a ROHM sales office for the product name package name pin number package code...

Page 840: ...ounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting con...

Page 841: ...ceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting contact a ROHM sales office for the product name package name pin number package code...

Page 842: ...unting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting cont...

Page 843: ...ceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting contact a ROHM sales office for the product name package name pin number package code...

Page 844: ...unting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting cont...

Page 845: ...unting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting cont...

Page 846: ...nting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting conta...

Page 847: ...ounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting con...

Page 848: ...unting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting cont...

Page 849: ...ounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting con...

Page 850: ...Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting co...

Page 851: ...e of Instruction execution cycle for details on how to read the table Example of Instruction execution cycle 1 2 1 2 2 3 1 3 2 4 5 Instruction Min execution cycle ROM reference cycle Effect of DSR acc...

Page 852: ...m8 1 1 AND Rn Rm 1 1 imm8 1 1 CMP Rn Rm 1 1 imm8 1 1 CMPC Rn Rm 1 1 imm8 1 1 MOV ERn ERm 1 1 imm7 1 1 MOV Rn Rm 1 1 imm8 1 1 OR Rn Rm 1 1 imm8 1 1 XOR Rn Rm 1 1 imm8 1 1 CMP ERn ERm 1 1 SUB Rn Rm 1 1...

Page 853: ...Rn EA 1 1 1 5 1 EA 1 1 1 5 1 ERm 1 1 2 1 1 5 1 1 Disp16 ERm 2 2 1 5 1 1 Disp6 BP 2 2 1 5 1 1 Disp6 FP 2 2 1 5 1 1 Dadr 2 2 1 5 1 1 XRn EA 2 2 2 10 1 EA 2 2 2 10 1 QRn EA 4 4 4 15 1 EA 4 4 4 15 1 ST ER...

Page 854: ...s Instructions Instruction Min execution cycle ROM reference cycle Effect of DSR access Effect of EA addressing No wait mode Wait mode No wait mode Wait mode ADD SP signed8 1 1 MOV ECSR Rm 1 1 ELR ERm...

Page 855: ...1 2 3 1 1 LR ELR 2 4 1 2 4 1 1 LR EA ELR 3 5 1 3 5 1 1 LR EPSW 2 3 1 2 3 1 1 LR EPSW EA 3 4 1 3 4 1 1 LR EPSW ELR 3 5 1 3 5 1 1 LR ELR EPSW EA 4 6 1 4 6 1 1 ERn 1 1 1 QRn 4 4 1 Rn 1 1 1 XRn 2 2 1 POP...

Page 856: ...CRm 1 1 1 5 1 1 EA CXRm 2 2 2 10 1 1 EA CXRm 2 2 2 10 1 1 EA Register Data Transfer Instructions Instruction Min execution cycle ROM reference cycle Effect of DSR access Effect of EA addressing No wai...

Page 857: ...it mode B Cadr 2 6 1 ERn 2 6 7 1 1 BL Cadr 2 6 1 ERn 2 6 7 1 1 1 When the immediately preceding instruction is for reading the data memory or not not the instruction for reading the data memory the in...

Page 858: ...ode MUL ERn Rm 9 9 DIV ERn Rm 17 17 Interrupts Instruction Min execution cycle ROM reference cycle Effect of DSR access Effect of EA addressing No wait mode Wait mode No wait mode Wait mode SWI snum 3...

Page 859: ...termine after the matching evaluation CL1 CL2 CL3 C12 1 0 F RSCL RSDA 5k or smaller LED P01 to P07 P10 to P17 P20 to P27 P30 to P33 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 PA...

Page 860: ...e area For details of Code Option Settings see Chapter 26 Code Option and make sure the setting data is correct It is recommended to fill unused areas with data 0xFFFF BRK instruction in the program m...

Page 861: ...ation 1 8 V or higher See Chapter 22 Voltage Level Supervisor VLS for the voltage level supervisor function At the power off the reset occurs when the power voltage VDD decreases below the power on re...

Page 862: ...d by the interrupt level ELEVEL of the program status word PSW master interrupt enable flag MIE the contents of the register IE0 to IE7 non maskable interrupt or maskable interrupt Since up to two ins...

Page 863: ...timer WDT reset to occur using the infinite loop to initialize the LSI See Section 5 3 4 Notes on Interrupt Routine with Interrupt Level Control Disabled Do not enable interrupts in a subroutine call...

Page 864: ...e to condensation When switching to the low speed crystal oscillation clock ensure to use the interrupt referring to the Section 6 3 5 Switching the Low speed Clock When using the low speed crystal os...

Page 865: ...e interrupt generation interval The time equivalent to max one clock of the system clock is required to reset the counter after writing to the LTBR register See Section 7 3 2 Low speed Time Base Count...

Page 866: ...the timer clock The external input signal EXTRGn which is input to the 16 bit timer is the signal that has passed the sampling controller of the external interrupt function The sampling of the extern...

Page 867: ...y has a significant error If window function enabled mode 1 or window function enabled mode 2 is chosen no WDT interrupt is generated A reset is generated in the first overflow The WDTMOD register is...

Page 868: ...nTUER SnROER and SnTOER bits during the communication Write them when the communication is stopped See Section 11 2 8 UARTn0 Mode Register UAn0MOD Be sure to set the UAn0MOD register while communicati...

Page 869: ...tions of other devices on the I 2 C bus Remain the power to this LSI when it works as a slave mode until the master device is powered off When using the master function do not connect multiple master...

Page 870: ...peration Timing If entering to the STOP STOP D mode while the slave mode is enabled first make sure that communication is not in progress from coincidence of address to reception of stop condition See...

Page 871: ...et the DCF bit when the transfer is disabled DCnEN bit 0 The DCnTN is not writable if the transfer is enabled DCnEN bit 1 When the specified transfer count is completed the channel corresponding bit o...

Page 872: ...the simplified RTC control register SRTCCON before writing to the SRTCMAS register It is recommended that data is written to the SRTCMAS register with word access After enabling the write operation us...

Page 873: ...tering STOP STOP D mode Max 30us When returning from STOP STOP D mode the interrupt is disable until the sampling clock LSCLK starts to be supplied The start up time for supplying clock is dependent o...

Page 874: ...eading the COMP0D bit when the comparator enables See Section 20 2 3 Comparator n Mode Register CMPnMOD n 0 1 In the STOP STOP D HALT H 1 mode no sampling is performed regardless of the values set in...

Page 875: ...nction like a reset IC start the VLS0 when the CPU initially runs at the low speed clock after the power up See Section 22 3 1 2 Interrupt Output Entering the STOP STOP D mode is not allowed during th...

Page 876: ...speed RC oscillation clock When using the channel 16 SACH16 enable the internal reference voltage temperature sensor and choose the internal reference voltage by setting VREFCON register See Section...

Page 877: ...a flash memory Confirm the end of programming by checking FDPRSTA bit of Flash Status Register FLASHSTA Erase data in the addresses in advance Programmed data without erase is unguaranteed Do not read...

Page 878: ...the programming ended The data flash area is unreadable during programming For data programming setting place two NOP instructions following the instruction used to set the programming data in the FL...

Page 879: ...connect EASE1000 when measuring the current consumption of the target system If EASE1000 remains connected the current consumption increases as the on chip debug circuit inside the LSI works for the c...

Page 880: ...package name pin number package code and desired mounting conditions reflow method temperature and times Notes for the package with exposed die pad The die pad is exposed on the bottom of WQFN package...

Page 881: ...Revision History...

Page 882: ...Series User s Manual Revision History FEUL62Q1000 R 1 REVISION HISTORY Document No Date Page Description Previous Edition Current Edition FEUL62Q1000 01 2018 12 11 ML62Q1300 1500 1700 Integrated Firs...

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