LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 237 / 882

ML62Q1000 Series User's Manual
Chapter 5 Interrupts
FEUL62Q1000 5-41
5.3.4 Notes on Interrupt Routine (with Interrupt Level Control Disabled)
Writing "0" to the ILE bit of the interrupt level control enable register (ILEN) causes the interrupt level control to be
disabled.
The description below shows notes on each of the following states when the interrupt level control is not in use.
Ÿ
When the sub routine is called/not called in the interrupt routine while execution of the maskable interrupt is in
progress (state A).
Ÿ
When the sub routine is called/not called in the interrupt routine while execution of a non-maskable interrupt is in
progress (state B).
State A: Maskable interrupt is being executed
A-1: When a subroutine is not called in an interrupt routine
A-1-1: When multiple interrupts are disabled
• When the script is written in the assembly language
• Processing immediately after the start of interrupt routine execution
No specific notes.
• Processing at the end of interrupt routine execution
Specify the RTI instruction to return the contents of the ELR register to the PC and those of the EPSW register
to PSW.
• When the script is written in C
Define the interrupt routine using the INTERRUPT pragma. Specify "1" in the category field. In this way,
appropriate codes are produced through the C compiler (CCU8).
Example of description: State A-1-1
For assembly language:
Intrpt_A-1-1; ; State of A-1-1
DI ; Disable interrupt
:
:
:
RTI ; Return PC from ELR
; Return PSW form EPSW
; End of interrupt routine
For C language:
static void Intrpt_A_1_1(void);
#pragma interrupt Intrpt_A_1_1 0x10 1
static void Intrpt_A_1_1(void)
{
_DI(); /* Disable interrupt */
:
} /* End of interrupt routine */