LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 193 / 882

ML62Q1000 Series User's Manual
Chapter 4 Power Management
FEUL62Q1000 4-27
Table 4-5 shows the wake-up time (restoring time) from the standby modes.
See Chapter 6 "Clock Generation Circuit" for details of the FHWUPT register.
Table 4-5 Wake-up Time from Standby Mode
Function Condition
CPU clock
restoring time
[T
RTCPU
]
Low-speed clock
restoring time
(Low-speed RC
oscillation)
[T
RTLS
]
High-speed clock restoring time (PLL
oscillation)
[T
RTPLL
]
FHWUPT=0x01 FHWUPT=0x00
HALT
mode
Low-speed CPU clock
High-speed clock OFF
No CRC calculation
Approximately
150
μs
Operation continued Stopped
Low-speed CPU clock
High-speed clock ON
or with CRC
calculation
Approximately
60
μs
Operation continued Operation continued
High-speed CPU clock - Operation continued Operation continued
HALT-H
mode
No CRC calculation T
RTPLL
+ 90
μs
Operation continued
Approximately
60
μs
Approx. 2.5 ms
With CRC calculation T
RTPLL
Operation continued
Approximately
60
μs
STOP
mode
Low-speed CPU clock T
RTLS
Approximately 320
μs
Approximately
305 μs
High-speed CPU clock T
RTPLL
Approximately 320 μs
Approximately
305 μs
STOP-D
mode
Low-speed CPU clock T
RTLS
Approximately 320 μs
Approximately
305 μs
High-speed CPU clock T
RTPLL
Approximately 320 μs
Approximately
305 μs
[Note]
Ÿ
If SYSTEMCLK is switched to high-speed after the STOP/STOP-D mode is released and before the
high-speed clock wake-up time passes, the CPU must wait to run the program because the clock supply
is suspended until the end of the wake-up time.
Ÿ
If peripheral circuits need to work in the HALT-H mode, choose the low-speed clock for the operating
clock.
Ÿ
When the FHWUPT register is set to "0x00", the PLL output clock is masked for approx.2.5 ms. HSCLK
will be supplied after the elapse of 2.5 ms. If HSCLK is selected for SYSTEMCLK, the SYSTEMCLK is
stopped for the time period.
Ÿ
When the FHWUPT register is set to "0x01", the frequency of PLL oscillation clock gradually increases
from approx. 1 MHz after the elapse of the wake-up time chosen by the FHWUPT register and reaches the
target frequency (16 MHz/24 MHz) chosen by the code option before approx. 2 ms elapse. The PLL
oscillation clock during this time period can be used for the SYSTEMCLK, however, accuracy of the
frequency is not guaranteed.