LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 689 / 882

ML62Q1000 Series User's Manual
Chapter 23 Successive Approximation Type A/D Converter
FEUL62Q1000
23-13
SA-ADC Control Register (SADCON) 23.2.7
SADCON is a special function register (SFR) used to control the operation of the A/D converter.
Address: 0xF82A(SADCONL/SADCON), 0xF82B(SADCONH)
Access: R/W
Access size: 8/16bit
Initial value:
0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Word
SADCON
Byte
SADCONH SADCONL
Bit
- - - - - - - - - - - - - -
SATGE
N
SARU
N
R/W R R R R R R R R R R R R R R R/W R/W
Initial
value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit No Bit symbol
name
Description
15 to 2 - Reserved
1 SATGEN This bit is used to enable starting the A/D conversion by the trigger events.
0: Disable the trigger operation (Initial value)
1: Enable the trigger operation
0 SARUN This bit is used to start or stop the A/D conversion.
Write "1" to this bit to start the A/D conversion, and "0" to stop it.
When "0" is written to SALP bit and the A/D conversion on the largest number of channel is
ended, this SARUN bit is automatically reset to "0".
When "1" is written to SALP, the A/D conversion repeats until the SARUN bit is reset to "0" by
the software.
0: Stop the A/D conversion (Initial value)
1: Start the A/D conversion
[Note]
Ÿ
Start the A/D conversion with one or more channels chosen by the SA-ADC enable registers (SADEN0
and SADEN1). If no channel is chosen, the operation does not start.
Ÿ
Enter STOP/STOP-D mode after checking SARUN bit is
"
0
"
, it does not enter the STOP/STOP-D mode
when the SARUN bit is
"
1
"
.
Ÿ
When SACK2 to 0 bits are set to 0x7, it takes max. 3 clocks of the low-speed clock(LSCLK) to start or
stop the A/D conversion after setting or resetting the SARUN bit.