LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 639 / 882

ML62Q1000 Series User's Manual
Chapter 20 Analog Comparator
FEUL62Q1000 20-7
20.2.3 Comparator n Mode Register (CMPnMOD: n=0,1)
CMPnMOD is a special function register (SFR) used to set the operation mode of the analog comparator.
Address: 0xF842(CMP0MODL/CMP0MOD), 0xF843(CMP0MODH),
0xF84A(CMP1MODL/CMP1MOD), 0xF84B(CMP1MODH),
Access: R/W
Access size: 8/16bit
Initial value:
0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Word
CMPnMOD
Byte
CMPnMODH CMPnMODL
Bit
- - - - - - -
CMPn
VREF
-
CMPn
DIV2
CMPn
DIV1
CMPn
DIV0
CMPn
CS1
CMPn
CS0
CMPn
E1
CMPn
E0
R/W R R R R R R R R/W R R/W R/W R/W R/W R/W R/W R/W
Initial
value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
No.
Bit symbol
name
Description
15 to 9 - Reserved bit
8 CMPnVREF This bit is used to choose the reference voltage of the analog comparator.
0: Use a reference voltage input from the CMPnM pin (initial value)
1: Uses the internal 0.8V reference voltage
7 - Reserved bit
6 to 4 CMPnDIV2 to
CMPnDIV0
These bits are used to choose frequency dividing ratio for the sampling clock in the analog
comparator.
000: No dividing (Initial value)
001: 1/2 of the sampling clock source
010: 1/4 of the sampling clock source
011: 1/8 of the sampling clock source
100: 1/16 of the sampling clock source
101: 1/32 of the sampling clock source
110: 1/64 of the sampling clock source
111: Do not use (No dividing)
3, 2 CMPnCS1
，
CMPnCS0
These bits are used to choose the sampling clock source in the analog comparator.
00: No sampling (Initial value)
01: Sampling with HSCLK
10: Sampling with LSCLK
11: Do not use (No sampling)
1, 0 CMPnE1
，
CMPnE0
This bit is used to choose the timing of interrupt request generation.
00: Disable the interrupt request generation (Initial value)
01: Falling-edge
10: Rising-edge
11: Both-edge