LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 701 / 882

ML62Q1000 Series User's Manual
Chapter 23 Successive Approximation Type A/D Converter
FEUL62Q1000
23-25
Figure 23-4 shows a setting example when one-time A/D conversion is performed using channel 1 and 0 starting by a
trigger event.
Figure 23-4 Example of A/D Conversion Setting (Start converting by a trigger event)
Set the mode of the reference voltage.
Set the A/D conversion mode. (SALP = 1)
Set the channel to be A/D-converted. (SADEN0=0x03)
Set the ENOSC bit of the FCON register to "1" to start supplying
the high-speed clock.
The high-speed clock is supplied after the oscillation stabilization
time has passed.
Set SASTS4 to 0 bits of SADTRG register.
Setting
start
Set the general-purpose port of AINn to the both input and output are
disable.
To use the voltage that is input from the V
REF
pin as the reference
voltage, set the mode of that disables the input and disables the output.
End
If enabling
SADINT
(SA-ADC interrupt), set the ESAD bit of the IE23
register to "1".
Execute the EI instruction to set the master interrupt enable flag (MIE) to "1".
Interrupt generated?
YES
NO
A/D conversion is
completed
Read the A/D conversion result.
(n=0, 1)
The SARUN bit is automatically cleared to "0".
Set IE register
Execute EI instruction
Set PnMOD0 to 7 registers
Set VREFCON register
Set SADMOD register
Set SADEN0 register
Set a trigger event source
Read SADRn register
Set FCON register
Set SADLMOD register
Set SADUPL register
Set SADLOL register
To use the upper/lower limit function for the conversion result, this
setting is required.
Enable the trigger event
The trigger event is
generated
Set SATGEN bit of SADCONL register to "1"