LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 234 / 882

ML62Q1000 Series User's Manual
Chapter 5 Interrupts
FEUL62Q1000 5-38
Table 5-2 List of Interrupt Sources (1/2)
Interrupt
source
number
(priority)
Register assignment
Interrupt
vector
address
Mask
External/
internal
source
Interrupt source
Interrupt
source
symbol
IRQ
(interrupt
request)
IE
(interrupt
enable)
ILC
(interrupt
level)
1 (high) IRQ0[0] - - 0x0008 Disabled
Internal
WDT interrupt WDTINT
2 - - - 0x000A Disabled -
-
3 IRQ0[6] IE0[6] ILC0[13:12] 0x000C Enabled
VLS0 interrupt VLS0INT
4 IRQ0[7] IE0[7] ILC0[15:14] 0x000E Enabled - -
5 IRQ1[0] IE1[0] ILC1[1:0] 0x0010 Enabled
External
External interrupt 0 EXI0INT
6 IRQ1[1] IE1[1] ILC1[3:2] 0x0012 Enabled
External interrupt 1 EXI1INT
7 IRQ1[2] IE1[2] ILC1[5:4] 0x0014 Enabled
External interrupt 2 EXI2INT
8 IRQ1[3] IE1[3] ILC1[7:6] 0x0016 Enabled
External interrupt 3 EXI3INT
9 IRQ1[4] IE1[4] ILC1[9:8] 0x0018 Enabled
External interrupt 4 EXI4INT
10 IRQ1[5] IE1[5] ILC1[11:10] 0x001A Enabled
External interrupt 5 EXI5INT
11 IRQ1[6] IE1[6] ILC1[13:12] 0x001C Enabled
External interrupt 6 EXI6INT
12 IRQ1[7] IE1[7] ILC1[15:14] 0x001E Enabled
External interrupt 7 EXI7INT
13 IRQ2[0] IE2[0] ILC2[1:0] 0x0020 Enabled
Internal
Clock backup interrupt CBUINT
14 IRQ2[1] IE2[1] ILC2[3:2] 0x0022 Enabled
DMA controller interrupt DMACINT
15 IRQ2[2] IE2[2] ILC2[5:4] 0x0024 Enabled
MCU status interrupt
*1
MCSINT
16 IRQ2[3] IE2[3] ILC2[7:6] 0x0026 Enabled
Serial communication unit 00 interrupt SIU00INT
17 IRQ2[4] IE2[4] ILC2[9:8] 0x0028 Enabled
Serial communication unit 01 interrupt SIU01INT
18 IRQ2[5] IE2[5] ILC2[11:10] 0x002A Enabled - -
19 IRQ2[6] IE2[6] ILC2[13:12] 0x002C Enabled
Successive approximation
type A/D converter interrupt
SADINT
20 IRQ2[7] IE2[7] ILC2[15:14] 0x002E Enabled - -
21 IRQ3[0] IE3[0] ILC3[1:0] 0x0030 Enabled External
Extended external interrupt EXTXINT
22 IRQ3[1] IE3[1] ILC3[3:2] 0x0032 Enabled
Internal
- -
23 IRQ3[2] IE3[2] ILC3[5:4] 0x0034 Enabled
I
2
C bus master 0 interrupt I2CM0INT
24 IRQ3[3] IE3[3] ILC3[7:6] 0x0036 Enabled I
2
C bus master 1 interrupt I2CM1INT
25 IRQ3[4] IE3[4] ILC3[9:8] 0x0038 Enabled
Functional timer 0 interrupt FTM0INT
26 IRQ3[5] IE3[5] ILC3[11:10] 0x003A Enabled
Functional timer 1 interrupt FTM1INT
27 IRQ3[6] IE3[6] ILC3[13:12] 0x003C Enabled
16-bit timer 0 interrupt TM0INT
28 IRQ3[7] IE3[7] ILC3[15:14] 0x003E Enabled
16-bit timer 1 interrupt TM1INT
29 IRQ4[0] IE4[0] ILC4[1:0] 0x0040 Enabled
Internal
I
2
C bus unit interrupt I2CU0INT
30 IRQ4[1] IE4[1] ILC4[3:2] 0x0042 Enabled
Serial communication unit 10 interrupt SIU10INT
31 IRQ4[2] IE4[2] ILC4[5:4] 0x0044 Enabled
Serial communication unit 11 interrupt SIU11INT
32 IRQ4[3] IE4[3] ILC4[7:6] 0x0046 Enabled - -
33 IRQ4[4] IE4[4] ILC4[9:8] 0x0048 Enabled
Functional timer 2 interrupt FTM2INT
34 IRQ4[5] IE4[5] ILC4[11:10] 0x004A Enabled
Functional timer 3 interrupt FTM3INT
*1 The MCU status interrupt occurs when one of the following interrupt requests is enabled:
- An interrupt request due to occurrence of a RAM parity error
- An interrupt request due to completion of an automatic CRC calculation.
- An interrupt request due to completion of erasing/writing to the data flash
Enabling/disabling each interrupt request can be controlled through SFRs. See Chapter 29 "Safety Function" for
details.