
ML62Q1000 Series User's Manual
Chapter 5 Interrupts
FEUL62Q1000
5-21
5.2.11 Current Interrupt Level Management Register (CIL)
CIL is a specific function register (SFR) to manage the priority level of the interrupt currently being processed by the
CPU.
After maskable or non-maskable interrupts to which the priority levels are specified by the interrupt level control
registers (ILC0 to 7) is accepted by the CPU, corresponding bits of CIL are automatically set to "1", indicate the
currently processing interrupt level.
Upcoming interrrupts request to the CPU which have lower priority(lower level) will be disabled.
When the multiple bits are "1" in the CIL, it indicates the CPU is processing the multiple interrupts.
Each bit of CIL is automatically set to "1", so it has to be cleared by the software when the interrupt process has been
ended. Clear the bit once by writing an arbitrary data at the last in the interrupt process, which resets a flag of CIL
corresponding to the highest level.
See the section "5.3.6 How to program the interrupt process when the interrupt level control is enabled".
Address:
0xF032(CIL)
Access:
R/W
Access size:
8bit
Initial value:
0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Word
-
Byte
-
CIL
Bit
-
-
-
-
-
-
-
-
CILN
-
-
-
CILM
3
CILM
2
CILM
1
CILM
0
R/W
R
R
R
R
R
R
R
R
R/W
R
R
R
R/W
R/W
R/W
R/W
Initial
value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit No.
Bit symbol
name
Description
7
CILN
This bit indicates the non-maskable interrupt is being processed or not.
0:
The non-maskable interrupt is not being processed (initial value)
1:
The non-maskable interrupt is being processed
6 to 4
-
Reserved bit
3
CILM3
This bit indicates the maskable interrupt with level 4 is being processed or not.
0:
The maskable interrupt with level 4 is not being processed (initial value)
1:
The maskable interrupt with level 4 is being processed
2
CILM2
This bit indicates the maskable interrupt with level 3 is being processed or not.
0:
The maskable interrupt with level 3 is not being processed (initial value)
1:
The maskable interrupt with level 3 is being processed
1
CILM1
This bit indicates the maskable interrupt with level 2 is being processed or not.
0:
The maskable interrupt with level 2 is not being processed (initial value)
1:
The maskable interrupt with level 2 is being processed
0
CILM0
This bit indicates the maskable interrupt with level 1 is being processed or not.
0:
The maskable interrupt with level 1 is not being processed (initial value)
1:
The maskable interrupt with level 1 is being processed
Summary of Contents for ML62Q1000 Series
Page 17: ...Chapter 1 Overview...
Page 112: ...Chapter 2 CPU and Memory Space...
Page 154: ...Chapter 3 Reset Function...
Page 166: ...Chapter 4 Power Management...
Page 196: ...Chapter 5 Interrupts...
Page 248: ...Chapter 6 Clock generation Circuit...
Page 274: ...Chapter 7 Low Speed Time Base Counter...
Page 291: ...Chapter 8 16 Bit Timer...
Page 320: ...Chapter 9 Functional Timer FTM...
Page 382: ...Chapter 10 Watchdog Timer...
Page 402: ...Chapter 11 Serial Communication Unit...
Page 456: ...Chapter 12 I2 C Bus Unit...
Page 491: ...Chapter 13 I2 C Master...
Page 512: ...Chapter 14 DMA Controller...
Page 531: ...Chapter 15 Buzzer...
Page 550: ...Chapter 16 Simplified RTC...
Page 559: ...Chapter 17 GPIO...
Page 594: ...Chapter 18 External Interrupt Function...
Page 612: ...Chapter 19 CRC Generator...
Page 632: ...Chapter 20 Analog Comparator...
Page 644: ...Chapter 21 D A Converter...
Page 655: ...Chapter 22 Voltage Level Supervisor...
Page 676: ...Chapter 23 Successive Approximation Type A D Converter...
Page 709: ...Chapter 24 Regulator...
Page 714: ...Chapter 25 Flash Memory...
Page 743: ...Chapter 26 Code Option...
Page 750: ...Chapter 27 LCD Driver...
Page 788: ...Chapter 28 On Chip Debug Function...
Page 795: ...Chapter 29 Safety Function...
Page 813: ...Appendix A...
Page 881: ...Revision History...