
ML62Q1000 Series User's Manual
Chapter 14
DMA
Controller
FEUL62Q1000
14-13
14.3 Description of Operation
The DMA controller can be used to transfer data between SFRs (special function registers) of peripheral circuits and data
memory (RAM) without involving the CPU.
After selecting the transfer unit, transfer count, transfer addressing, and transfer trigger followed by enabling the DMA
transfer, once the specified transfer count is completed, the DMA controller interrupt request is generated.
14.3.1 Procedure to Use DMA Controller
The following chart shows the DMA controller setting procedure.
Figure 14-3 DMA Setting Procedure
n=0 or 1
Start
Set with the DCnTN register
Once to 1024 times
Set with DCnSAMD0 and DCnSAMD1 bits of the DCnMOD
register
Select the address fixed mode, increment addressing mode,
or decrement addressing mode
Set with the DCnSA register
Initialize the peripheral used as the trigger
Set the DMA transfer trigger with DCnTRG0 to DCnTRG4 of the
DCnMOD register
Set with the DCnDA register
Set with the DCnDS bit of the DCnMOD register
8-bit or 16-bit
Set with the DCF bit of the DCEN register
Channel free or channel fixed
Set with the DCnEN bit of the DCEN register
(DCnEN=1)
DMA trigger generated -> DMA transfer completed -> DMA
interrupt request wait
Enable the DMA
interrupt
Set with the EDMA bit (EDMA="1")
Transfer count
setting
Transfer unit
setting
Transfer destination
address setting
Addressing mode
setting
Setting for channel
status during
transmission
Transfer source
address setting
Trigger setting
Transmit enable
setting
Other processing
Summary of Contents for ML62Q1000 Series
Page 17: ...Chapter 1 Overview...
Page 112: ...Chapter 2 CPU and Memory Space...
Page 154: ...Chapter 3 Reset Function...
Page 166: ...Chapter 4 Power Management...
Page 196: ...Chapter 5 Interrupts...
Page 248: ...Chapter 6 Clock generation Circuit...
Page 274: ...Chapter 7 Low Speed Time Base Counter...
Page 291: ...Chapter 8 16 Bit Timer...
Page 320: ...Chapter 9 Functional Timer FTM...
Page 382: ...Chapter 10 Watchdog Timer...
Page 402: ...Chapter 11 Serial Communication Unit...
Page 456: ...Chapter 12 I2 C Bus Unit...
Page 491: ...Chapter 13 I2 C Master...
Page 512: ...Chapter 14 DMA Controller...
Page 531: ...Chapter 15 Buzzer...
Page 550: ...Chapter 16 Simplified RTC...
Page 559: ...Chapter 17 GPIO...
Page 594: ...Chapter 18 External Interrupt Function...
Page 612: ...Chapter 19 CRC Generator...
Page 632: ...Chapter 20 Analog Comparator...
Page 644: ...Chapter 21 D A Converter...
Page 655: ...Chapter 22 Voltage Level Supervisor...
Page 676: ...Chapter 23 Successive Approximation Type A D Converter...
Page 709: ...Chapter 24 Regulator...
Page 714: ...Chapter 25 Flash Memory...
Page 743: ...Chapter 26 Code Option...
Page 750: ...Chapter 27 LCD Driver...
Page 788: ...Chapter 28 On Chip Debug Function...
Page 795: ...Chapter 29 Safety Function...
Page 813: ...Appendix A...
Page 881: ...Revision History...