LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 500 / 882

ML62Q1000 Series User's Manual
Chapter 13 I2C Master
FEUL62Q1000 13-9
13.2.6 I
2
C Master n Mode Register (I2MnMOD: n=0,1)
I2UM0MOD is a special function register (SFR) used to set the operation mode.
Address: 0xF6EA(I2M0MODL/I2M0MOD), 0xF6EB(I2M0MODH),
0xF6FA(I2M1MODL/I2M1MOD), 0xF6FB(I2M1MODH)
Access: R/W
Access size: 8/16bit
Initial value:
0x0200
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Word
I2MnMOD
Byte
I2MnMODH I2MnMODL
Bit
- - - - - -
I2MnC
D1
I2MnC
D0
- -
I2MnS
YN
I2MnD
W1
I2MnD
W0
I2MnM
D1
I2MnM
D0
I2MnE
N
R/W R R R R R R R/W R/W R R R/W R/W R/W R/W R/W R/W
Initial
value
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Bit
No.
Bit symbol
name
Description
15 to
10
- Reserved bit
9, 8 I2MnCD1,
I2MnCD0 These bits are used to choose the I
2
C operating clock.
0 0: HSCLK
0 1: 1/2HSCLK
1 0: 1/4HSCLK (Initial value)
1 1: Do not use
7, 6
- Reserved bit
5 I2MnSYN This bit is used to choose whether to or not to use the clock stretch (handshake) function. Set
this bit to "1" when using the clock stretch function. Setting this bit to "1" monitors the I
2
C bus,
therefore the communication speed gets lower depending on the load of I
2
C bus.
0: Not use the clock stretch function (Initial value)
1: Use the clock stretch function
4, 3 I2MnDW1
，
I2MnDW0
These bits are used to set the communication speed reduction rate of the I
2
C bus master.
Specify this bit not so that the communication speed exceeds 100 kbps/400kbps/1 Mbps.
When LSCLK or 1/8 LSCLK is chosen by the I2UM0CD2 to 0 bits, "No communication speed
reduction" is chosen regardless the setting of I2UM0DW1 to 0 bits.
0 0: No communication speed reduction (initial value)
0 1: 10% communication speed reduction
1 0: 20% communication speed reduction
1 1: 30% communication speed reduction
2, 1 I2MnMD1,
I2MnMD0 These bits are used to set the communication speed of the I
2
C bus unit in the master mode.
0 0: Standard mode (initial value) (100 kbps*)
0 1: Fast mode (400 kbps*)
1 0: 1Mbps mode (1Mbps*)
1 1: 1Mbps mode (1Mbps*)
* : When I2MnCD1 to 0 bits are "00" and I2MnSYN bit is "0".
0 I2MnEN This bit is used to enable the master operation. When "1" is written to this bit, the I2MnST bit
can be set and the I2MnBB bit starts operation. When "0" is written to this bit, the I
2
C master
stops operation and the all related registers are initialized.
0: Stop the I
2
C master operation (initial value)
1: Enable the I
2
C master operation