LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 395 / 882

ML62Q1000 Series User's Manual
Chapter 10 Watchdog Timer
FEUL62Q1000 10-13
The following figure shows an operation timing overview of the window function disabled mode
Figure 10-6
Overview of Operation Timing in Window Function Disabled Mode
The following table shows the WDT counter clear enabled period in the window function disabled mode.
Table 10-3 WDT Counter Clear Enabled Period in Window Function Disabled Mode
WDT2 WDT1 WDT0
Overflow
period
(T
WOV
)
*1
WDT reset
generation
time
*1
WDT counter clear enabled period
(T
WCL
)
*1*2
0 0 0
7.8 ms 15.6 ms
≈ Overflow period
0 0 1
15.6 ms 31.3 ms
≈ Overflow period
0 1 0
31.3 ms 62.5 ms
≈ Overflow period
0 1 1
62.5 ms 125 ms
≈ Overflow period
1 0 0
125 ms 250 ms
≈ Overflow period
1 0 1
500 ms 1000 ms
≈ Overflow period
1 1 0
2000 ms 4000 ms
≈ Overflow period
1 1 1
8000 ms 16000 ms
≈ Overflow period
*1: Time when the WDTCLK is 1 .024kHz. If choosing RC1K oscillation for the WDTCLK, the frequency has a
significant error.
*2:
The clear processing is enable for two clocks of the WDTCLK (2ms when the WDTCLK is
1.024kHz) before the WDT gets overflowed.
WDT counter value
0
Time
Overflow period (T
WOV
)
Overflow period
(T
WOV
)
Overflow period
(T
WOV
)
WDT cleared
WDT interrupt generated
WDT reset generation time
Clear enabled period (T
WCL
)