LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 160 / 882

ML62Q1000 Series User's Manual
Chapter 3 Reset Function
FEUL62Q1000 3-6
3.2.2 Reset status register (RSTAT)
RSTAT is a special function register (SFR) to indicate the cause of occurrence of a reset.
When a reset occurs, only the bit that indicates the cause of the reset occurred is set to "1". Other bits (except the INITE
bit) retain values before occurrence of the reset. After identifying the cause of the reset, write "0xFFFF" to the RSTAT
register to initialize it for preparing the next reset.
Address: 0xF058 (RSTATL/RSTAT), 0xF059 (RSTATH)
Access: R/W
Access size: 8/16 bits
Initial value:
Undefined
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Word RSTAT
Byte RSTATH RSTATL
Bit - - - - - - - BRKR INITE RSTR - VLS0R WDTWR WDTR - POR
R/W R R R R R R R R/W R R/W R R/W R/W R/W R R/W
Initial
value
0 0 0 0 0 0 0 0/1 0 0/1 0 0/1 0/1 0/1 0 0/1
Bit
No.
Bit symbol
name
Description
15 to 9 - Reserved bits
8 BRKR A bit to indicate that a CPU reset has occurred through the BRK instruction execution by the
CPU.
This bit is initialized to "0" when "1" is written.
0: No CPU reset through the BRK instruction occurred
1: CPU reset by BRK instruction occurred
7 INITE A read-only bit to indicate that an abnormality occurred in starting LSI.
If this bit is set to "1", restart the LSI by causing a reset to occur with the reset input pin reset
or power-on.
0: LSI started-up normally
1: Abnormality occurred in start-up of LSI
6 RSTR A bit to indicate that a reset input pin reset has occurred.
This bit is initialized to "0" when "1" is written.
0: No reset input pin reset occurred
1: Reset input pin reset occurred
5 - Reserved bits
4 VLS0R A bit to indicate that a voltage level supervisor reset has occurred.
This bit is initialized to "0" when "1" is written.
0: No voltage level supervisor reset occurred
1: Voltage level supervisor reset occurred
3 WDTWR A bit to indicate that a watchdog timer (WDT) invalid clear reset has occurred.
This bit is initialized to "0" when "1" is written.
0: No watchdog timer invalid clear reset occurred
1: Watchdog timer invalid clear reset occurred
2 WDTR A bit to indicate that a watchdog timer (WDT) overflow reset has occurred.
This bit is initialized to "0" when "1" is written.
0: No watchdog timer reset occurred
1: Watchdog timer reset occurred
1 - Reserved bits