LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 392 / 882

ML62Q1000 Series User's Manual
Chapter 10 Watchdog Timer
FEUL62Q1000 10-10
10.3.1 How to Clear WDT Counter
The WDT counter can be cleared by writing "0x5A" to the WDTCON register with the WDP bit set to "0", then writing
"0xA5" to the WDTCON register with the WDP bit set to "1" while WDT counter clearing is enabled.
The WDP bit is reset to "0" when the system is reset as well as when the WDT counter overflows. It is reversed every
time data is written to the WDTCON register.
The following diagram shows the WDT counter clearing timing chart.
Figure 10-3 WDT Counter Clearing Timing Chart
The following description shows a sample program script of the watchdog timer.
void wdt_clear( void )
{
unsigned char pswval;
if(WDTCLR1 == 1) { // Checking presence of pending clearing process
return;
};
if(WDTCLR2== 1) { // Checking whether clearing process is pending or completed
return;
};
pswval = s_drvcommon_getPSW(); // Saving PSW
_DI(); // Interrupt disabled (clearing MIE bit)
do {
WDTCON = 0x5A; // WDT counter clearing
} while (WDP != 1 );
WDTCON = 0xA5;
if ((pswval & 0x08) != 0) { // Confirming MIE bit
_EI(); // Interrupt enabled (setting MIE bit)
}
static unsigned char s_drvcommon_getPSW( void ){
#pragma asm
mov r0,psw
rt
#pragma endasm
}
Figure 10-4 Sample Program Script of Watchdog Timer
Writing of "0xA5"
System clock
WDTCON Write
WDTCLR1
WDT counter
WDP bit
WDTCLR2
WDT clock
0 n n-1 n-2
Writing of "0x5A"