
ML62Q1000 Series User's Manual
Chapter 17 General Purpose Port
FEUL62Q1000
17-31
17.3 Description of Operation
17.3.1 Input
Each pin of port n sets the PnmIE bit of the PnMODm register to enter the state where input is enabled.
In the state with input enabled, the pin level can be read using the PnDI register.
In addition, pull-up can be enabled by setting the PnmPU bit of the PnMODm register.
At a system reset, input disabled and no pull-up are selected as the initial status.
n: Port number 0 to 9, A, B
m: Bit number 0 to 7
17.3.2 Output
Each pin of port n sets the PnmOD bit of the PnMODm register to choose either CMOS output or N-channel open drain
output as an output type and sets PnmOE bit of the PnMODm register to enter the state where output is enabled.
In the state with output enabled, "L" or "H" level is output to each pin of the general-purpose port (GPIOn) according to
the value set in the PnDO register.
At a system reset, output disabled and CMOS output are selected as the initial status.
n: Port number 0 to 9, A, B
m: Bit number 0 to 7
17.3.3 Primary Functions Other than Input/Output Function
External input (EXI0 to EXI11) can be used as the primary function other than the input/output function.
When using EXI0 to EXI11 as external interrupt input and the external clock inputs of the 16-bit timer or external
trigger/external clock input of the functional timer, set the PnMODm register of the applicable port to input enabled
(PnmIE bit="1").
See Chapter 18 "External Interrupt Control" for external interrupts, Chapter 8 "16-Bit Timer" for external clock input of
the 16-bit timer, and Chapter 9 "Functional Timer" for external trigger/external clock input of the functional timer.
n: Port number 0 to 9, A, B
m: Bit number 0 to 7
17.3.4 Shared Function
Each pin of port n can use secondary to octonary functions as the shared function.
Set PnmMD3 to PnmMD0 bits of the PnMODm register to choose each of the secondary to octonary functions.
For the usable shared function, see Table 1-7 "ML62Q1300 Group Pin List", Table 1-8 "ML62Q1500 Group Pin List"
and Table 1-9 "ML62Q1700 Group Pin List".
n: Port number 0 to 9, A, B
m: Bit number 0 to 7
Summary of Contents for ML62Q1000 Series
Page 17: ...Chapter 1 Overview...
Page 112: ...Chapter 2 CPU and Memory Space...
Page 154: ...Chapter 3 Reset Function...
Page 166: ...Chapter 4 Power Management...
Page 196: ...Chapter 5 Interrupts...
Page 248: ...Chapter 6 Clock generation Circuit...
Page 274: ...Chapter 7 Low Speed Time Base Counter...
Page 291: ...Chapter 8 16 Bit Timer...
Page 320: ...Chapter 9 Functional Timer FTM...
Page 382: ...Chapter 10 Watchdog Timer...
Page 402: ...Chapter 11 Serial Communication Unit...
Page 456: ...Chapter 12 I2 C Bus Unit...
Page 491: ...Chapter 13 I2 C Master...
Page 512: ...Chapter 14 DMA Controller...
Page 531: ...Chapter 15 Buzzer...
Page 550: ...Chapter 16 Simplified RTC...
Page 559: ...Chapter 17 GPIO...
Page 594: ...Chapter 18 External Interrupt Function...
Page 612: ...Chapter 19 CRC Generator...
Page 632: ...Chapter 20 Analog Comparator...
Page 644: ...Chapter 21 D A Converter...
Page 655: ...Chapter 22 Voltage Level Supervisor...
Page 676: ...Chapter 23 Successive Approximation Type A D Converter...
Page 709: ...Chapter 24 Regulator...
Page 714: ...Chapter 25 Flash Memory...
Page 743: ...Chapter 26 Code Option...
Page 750: ...Chapter 27 LCD Driver...
Page 788: ...Chapter 28 On Chip Debug Function...
Page 795: ...Chapter 29 Safety Function...
Page 813: ...Appendix A...
Page 881: ...Revision History...