
ML62Q1000 Series User's Manual
Chapter 6
Clock Generation Circuit
FEUL62Q1000
6-7
6.2.3 Low-speed Clock Mode Register (FLMOD)
FLMOD is a specific function register (SFR) to control the low-speed clock (LSCLK).
The FLMOD is initialized by only the Power-On-Reset.
This register is unavailable on the ML62Q1300 group.
Address:
0xF004 (FLMOD)
Access:
R/W
Access size: 8bit
Initial value: 0x00
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Word
-
Byte
-
FLMOD
Bit
-
-
-
-
-
-
-
-
LMO
D1
LMO
D0
-
LFLT
SEL
-
-
LOSC
M1
LOSC
M0
R/W
R
R
R
R
R
R
R
R
R/W
R/W
R
R/W
R
R
R/W
R/W
Initial
value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit No.
Bit symbol
name
Description
15 to 8
-
Reserved bit
7,6
LMOD1,
LMOD0
These bits are used to choose the mode of low-speed crystal oscillation circuit.
These bits are unchangeable when the LOSCM0 bit is "1".
00: Standard mode (Initial value)
01: Low power consumption mode
10: Do not use
11: Tough mode
The low power consumption mode reduces the current consumption by lowering the
oscillation margin than the standard mode. The tough mode increases the oscillation
margin and heightens the resistance against leakage between the pins, increases the
current consumption.
5
-
Reserved bit
4
LFLTSEL
This bit is used to have a noise filter in the low-speed oscillation circuit.
This bit are unchangeable when the LOSCM0 bit is "1".
0:
Use the noise filter (Initial value)
1:
Do not use the noise filter
3
-
Reserved bit
1,0
LOSCM1,
LOSCM0
This bit is used to choose the clock source of low-speed clock (LSCLK). Low-speed RC
oscillation (approx.32.768kHz), Low-speed crystal oscillation (32.768kHz) or Low-speed
external clock (32.768kHz) can be chosen.
00: Low-speed RC oscillation clock (Initial)
01: Low-speed Crystal oscillation clock
10: Do not use (Low-speed RC oscillation clock)
11: Low-speed External clock input(XT1 pin)
The low-speed crystal oscillation clock and the low-speed external clock mode are not
available to switch directly each other. Change the mode to the low-speed RC oscillation
clock once.
[Note]
Ÿ
Do not change the LOSCM1 bit ad LOSCM0 bit when the ENOSC bit is
"
1
"
, otherwise the operation is
unguaranteed.
Summary of Contents for ML62Q1000 Series
Page 17: ...Chapter 1 Overview...
Page 112: ...Chapter 2 CPU and Memory Space...
Page 154: ...Chapter 3 Reset Function...
Page 166: ...Chapter 4 Power Management...
Page 196: ...Chapter 5 Interrupts...
Page 248: ...Chapter 6 Clock generation Circuit...
Page 274: ...Chapter 7 Low Speed Time Base Counter...
Page 291: ...Chapter 8 16 Bit Timer...
Page 320: ...Chapter 9 Functional Timer FTM...
Page 382: ...Chapter 10 Watchdog Timer...
Page 402: ...Chapter 11 Serial Communication Unit...
Page 456: ...Chapter 12 I2 C Bus Unit...
Page 491: ...Chapter 13 I2 C Master...
Page 512: ...Chapter 14 DMA Controller...
Page 531: ...Chapter 15 Buzzer...
Page 550: ...Chapter 16 Simplified RTC...
Page 559: ...Chapter 17 GPIO...
Page 594: ...Chapter 18 External Interrupt Function...
Page 612: ...Chapter 19 CRC Generator...
Page 632: ...Chapter 20 Analog Comparator...
Page 644: ...Chapter 21 D A Converter...
Page 655: ...Chapter 22 Voltage Level Supervisor...
Page 676: ...Chapter 23 Successive Approximation Type A D Converter...
Page 709: ...Chapter 24 Regulator...
Page 714: ...Chapter 25 Flash Memory...
Page 743: ...Chapter 26 Code Option...
Page 750: ...Chapter 27 LCD Driver...
Page 788: ...Chapter 28 On Chip Debug Function...
Page 795: ...Chapter 29 Safety Function...
Page 813: ...Appendix A...
Page 881: ...Revision History...