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8XC196NT USER’S MANUAL
4-2
Because the four MSBs of the internal address can take any values without changing the external
address, these four bits effectively produce 16 copies of the 1-Mbyte address space, for a total of
16 Mbytes in 256 pages, 00H–FFH (Figure 4-1). For example, page 01H has 15 duplicates: 11H,
21H, ..., F1H. This duplication is termed wraparound, implying that the sixteen 1-Mbyte areas of
the memory space are overlaid. The shaded areas in Figure 4-1 represent the overlaid areas.
Figure 4-1. 16-Mbyte Address Space
The memory pages of interest are 00H–0FH and FFH. Pages 01H–0EH are external memory with
unspecified contents; they can store either code or data. Pages 00H and FFH, shown in Figure
4-2, have special significance. Page 00H contains the register file and the special-function regis-
ters (SFRs), while page FFH contains special-purpose memory (chip configuration bytes and in-
terrupt vectors) and program memory. The device fetches its first instruction from location
FF2080H. Addresses in page FFH exist only in the internal 24-bit address space.
The implementation of page FFH in the 87C196NT differs from that in the 80C196NT. For the
87C196NT, locations FF2000–FF9FFFH are implemented by 32 Kbytes of internal OTPROM
and the remainder of page FFH (FFA000–FFFFFFH) is implemented by external memory in page
0FH. For the 80C196NT, which has no internal OTPROM, all of page FFH is implemented by
external memory in page 0FH.
NOTE
Because the device has 24 bits of address internally, all programs must be
written as though the device uses all 24 bits. The device resets from page FFH,
so all code must originate from this page. (Use the assembler directive, “cseg
at 0FFxxxxH.”) This is true even if the code is actually stored in external
memory.
A2541-02
16 Mbyte
FFH
•
•
•
F1H
F0H
3 Mbyte
2FH
•
•
•
21H
20H
2 Mbyte
1FH
•
•
•
11H
10H
1 Mbyte
0FH
•
•
•
01H
00H
Externally
Addressable
•
•
•
Summary of Contents for 8XC196NT
Page 1: ...8XC196NT Microcontroller User s Manual...
Page 2: ...8XC196NT Microcontroller User s Manual June 1995 Order Number 272317 003...
Page 22: ...1 Guide to This Manual...
Page 23: ......
Page 35: ......
Page 36: ...2 Architectural Overview...
Page 37: ......
Page 49: ......
Page 50: ...3 Programming Considerations...
Page 51: ......
Page 66: ...4 Memory Partitions...
Page 67: ......
Page 104: ...5 Standard and PTS Interrupts...
Page 105: ......
Page 147: ......
Page 148: ...6 I O Ports...
Page 149: ......
Page 176: ...7 Serial I O SIO Port...
Page 177: ......
Page 194: ...8 Synchronous Serial I O SSIO Port...
Page 195: ......
Page 211: ......
Page 212: ...9 Slave Port...
Page 213: ......
Page 231: ......
Page 232: ...10 Event Processor Array EPA...
Page 233: ......
Page 270: ...11 Analog to digital Converter...
Page 271: ......
Page 291: ......
Page 292: ...12 Minimum Hardware Considerations...
Page 293: ......
Page 306: ...13 Special Operating Modes...
Page 307: ......
Page 317: ......
Page 318: ...14 Interfacing with External Memory...
Page 319: ......
Page 362: ...15 Programming the Nonvolatile Memory...
Page 363: ......
Page 408: ...A Instruction Set Reference...
Page 409: ......
Page 476: ...B Signal Descriptions...
Page 477: ......
Page 493: ......
Page 494: ...C Registers...
Page 495: ......
Page 565: ......
Page 566: ...Glossary...
Page 567: ......
Page 580: ...Index...
Page 581: ......
Page 597: ......