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8XC196NT USER’S MANUAL
10-22
6
CE
Compare Enable
Determines whether the EPA channel operates in capture or compare
mode.
0 = capture mode
1 = compare mode
5:4
M1:0
EPA Mode Select
In capture mode, specifies the type of event that triggers an input capture.
In compare mode, specifies the action that the EPA executes when the
reference timer matches the event time.
M1
M0
Capture Mode Event
0
0
no capture
0
1
capture on falling edge
1
0
capture on rising edge
1
1
capture on either edge
M1
M0
Compare Mode Action
0
0
no output
0
1
clear output pin
1
0
set output pin
1
1
toggle output pin
3
RE
Re-enable
Re-enable applies to the compare mode only. It allows a compare event
to continue to execute each time the event-time register (EPA
x
_TIME)
matches the reference timer rather than only upon the first time match.
0 = compare function is disabled after a single event
1 = compare function always enabled
EPA
x
_CON (Continued)
x
= 0–9
Address:
Reset State:
See Table 10-2 on
page 10-3
F700H (
x
= 1 & 3)
00H(
x
= 0, 2, 4–9)
The EPA control (EPA
x
_CON) registers control the functions of their assigned capture/compare
channels. The registers for EPA0, EPA2, and EPA4–9 are identical. The registers for EPA1 and EPA3
have an additional bit, the remap bit. This added bit (bit 8) requires an additional byte, so EPA1_CON
and EPA3_CON must be addressed as words, while the others can be addressed as bytes.
15
8
x
= 1, 3
—
—
—
—
—
—
—
RM
7
0
TB
CE
M1
M0
RE
AD
ROT
ON/RT
7
0
x
= 0, 2, 4–9
TB
CE
M1
M0
RE
AD
ROT
ON/RT
Bit
Number
Bit
Mnemonic
Function
†
These bits apply to the EPA1_CON and EPA3_CON registers only.
Figure 10-10. EPA Control (EPA
x_CON) Registers (Continued)
Summary of Contents for 8XC196NT
Page 1: ...8XC196NT Microcontroller User s Manual...
Page 2: ...8XC196NT Microcontroller User s Manual June 1995 Order Number 272317 003...
Page 22: ...1 Guide to This Manual...
Page 23: ......
Page 35: ......
Page 36: ...2 Architectural Overview...
Page 37: ......
Page 49: ......
Page 50: ...3 Programming Considerations...
Page 51: ......
Page 66: ...4 Memory Partitions...
Page 67: ......
Page 104: ...5 Standard and PTS Interrupts...
Page 105: ......
Page 147: ......
Page 148: ...6 I O Ports...
Page 149: ......
Page 176: ...7 Serial I O SIO Port...
Page 177: ......
Page 194: ...8 Synchronous Serial I O SSIO Port...
Page 195: ......
Page 211: ......
Page 212: ...9 Slave Port...
Page 213: ......
Page 231: ......
Page 232: ...10 Event Processor Array EPA...
Page 233: ......
Page 270: ...11 Analog to digital Converter...
Page 271: ......
Page 291: ......
Page 292: ...12 Minimum Hardware Considerations...
Page 293: ......
Page 306: ...13 Special Operating Modes...
Page 307: ......
Page 317: ......
Page 318: ...14 Interfacing with External Memory...
Page 319: ......
Page 362: ...15 Programming the Nonvolatile Memory...
Page 363: ......
Page 408: ...A Instruction Set Reference...
Page 409: ......
Page 476: ...B Signal Descriptions...
Page 477: ......
Page 493: ......
Page 494: ...C Registers...
Page 495: ......
Page 565: ......
Page 566: ...Glossary...
Page 567: ......
Page 580: ...Index...
Page 581: ......
Page 597: ......