Intel 8XC196NT, User Manual

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6-17
I/O PORTS
With the open-drain configuration (BUS CONTROL SELECT set and P34_DRV cleared) and
Px_REG set, the pin can be used as an input. The signal on the pin is latched in the Px_PIN reg-
ister. The pins can be read, making it easy to see which pins are driven low by the device and
which are driven high by external drivers while in open-drain mode. Table 6-13 is a logic table
for ports 3 and 4 as I/O.
6.4.2 Using Ports 3 and 4 as I/O
Ports 3 and 4 must be configured entirely as complementary or open-drain ports; their pins cannot
be configured individually. To configure a port, first select complementary or open-drain mode
by writing to P34_DRV. Set a bit to configure the port as complementary; clear a bit to configure
the port as open-drain.
To use a port pin as an output, write the output data to the corresponding Px_REG bit. In comple-
mentary mode, a pin is driven high when the corresponding Px_REG bit is set. In open-drain
mode, you need to connect an external pull-up resistor. When the device requires access to exter-
nal memory, it takes control of the port and drives the address/data bit onto the pin. The ad-
dress/data bit replaces your output during this time. When the external access is completed, the
device restores your data onto the pin.
To use a port pin as an input, first clear the corresponding P34_DRV bit to configure the port as
open-drain. Next, set the corresponding Px_REG bit to drive the pin to a high-impedance state.
You may then read the pin’s input value in the Px_PIN register. When the device requires access
to external memory, it takes control of the port. You must configure the input source to avoid con-
tention on the bus.
Table 6-13. Logic Table for Ports 3 and 4 as I/O
Configuration Complementary Open-drain
P34_DRV 1 1 0 0
P x _REG 0 1 0 1
Q1 off on off off
Q2 on off on off
P x_ PIN 0 1 0 high-impedance