Intel 8XC196NT, User Manual

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14-17
INTERFACING WITH EXTERNAL MEMORY
14.5 WAIT STATES (READY CONTROL)
An external device can use the READY input to request wait states in addition to the wait states
that are generated internally by the 8XC196NT device. When an address is placed on the bus for
an external bus cycle, the external device can pull the READY signal low to indicate it is not
ready. In response, the bus controller inserts wait states to lengthen the bus cycle until the external
device raises the READY signal. Each wait state adds one CLKOUT period (i.e., one state time
or 2T
OSC
) to the bus cycle.
After reset and until CCB1 is read, the bus controller always inserts three wait states into bus cy-
cles. Then, until P5.6 has been configured to operate as the READY signal, the internal ready
control bits (IRC2:0) control the wait states. If IRC2:0 are all set during CCB0 and CCB1 fetch,
READY (P5.6) is configured as a special-function input. If port 5 is initialized after reset, you
must ensure that P5.6 remains configured as the READY input. If P5.6 is configured as a port
pin, the READY input to the device is equal to zero. This will cause an infinite number of wait
states to be inserted into bus cycles and the chip to lock up.
After the CCB1 fetch, the internal ready control circuitry allows slow external memory devices
to increase the length of the read and write bus cycles. If the external memory device is not ready
for access, it pulls the READY signal low and holds it low until it is ready to complete the oper-
ation, at which time it releases READY. While READY is low, the bus controller inserts wait
states into the bus cycle.
The internal ready control bits (IRC2:0) define the maximum number of wait states that will be
inserted. (The IRC2:0 bits are defined in Figures 14-1 and 14-2.) When all three bits are set, the
bus controller inserts wait states until the external memory device releases the READY signal.
Otherwise, the bus controller inserts wait states until either the external memory device releases
the READY signal or the number of wait states equals the number (0, 1, 2, or 3) specified by the
CCB bit settings.
When selecting infinite wait states, be sure to add external hardware to count wait states and re-
lease READY within a specified period of time. Otherwise, a defective external device could tie
up the address/data bus indefinitely.
NOTE
Ready control is valid only for external memory; you cannot add wait states
when accessing internal ROM.