Intel 8XC196NT, User Manual

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8XC196NT USER’S MANUAL
15-8
15.4 PROGRAMMING PULSE WIDTH
The programming pulse width is controlled in different ways depending on the programming
mode. In all cases, the pulse width must be at least 100 µs for successful programming. In slave
programming mode, the pulse width is controlled by the PALE# signal. In auto programming
mode, it is loaded from the external EPROM into the PPW register. In serial port programming
mode, it is loaded from the test ROM into the SP_PPW register. In run-time programming mode,
your software controls the pulse width.
The PPW and SP_PPW registers (Figure 15-2) are identical except for their locations and default
values. Both are word registers and both require that the most-significant bit always be set; the
remaining bits constitute the PPW_VALUE. To determine the correct PPW_VALUE for the fre-
quency of the device, use the following formula and round the result to the next higher integer.
where:
PPW_VALUE is a 15-bit word
F
OSC
is the input frequency on XTAL1, in MHz
Time is the duration of the programming pulse, in µs
The following two examples calculate the PPW_VALUE for a 100-µs pulse width with an 8-MHz
and a 16-MHz crystal, respectively.
Table 15-4. UPROM Programming Values and Locations for Slave Mode
To set this bit Write this value To this location
DEI 08H 0718H
DED 04H 0758H
OFD
†
01H 0778H
†
Intel manufacturing uses location FF2016H to determine whether to program the OFD bit. Customers with
QROM or MROM codes who desire the OFD feature should equate location FF2016H to the value 0CDEH.
PPW_VALUE
F
osc
Time
×
144
--------------------------------
1 – =
PPW_VALUE
8 100
×
144
-------------------
1 –
800
144
----------
1 – 4.5552 5
≈
05H = = = =
PPW_VALUE
16 100
×
144
----------------------
1
–
1600
144
-------------
1
–
10.11 11
≈
0BH
= = = =