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5-37
STANDARD AND PTS INTERRUPTS
When the next timer match occurs, the PTS cycle (Figure 5-17) increments EPA0_TIME by T1
(if TBIT is zero (output = 0)) or T2 – T1 (if TBIT is one (output = 1)). (Note that although the
values of the EPA0 output and TBIT are the same in this example, these two values are unrelated.
To establish the initial value of the output, set or clear P1_REG.x.)
The PWM toggle mode has the advantage of using only one EPA channel. However, if the wave-
form edges are close together, the PTS may take too long and miss setting up the next edge. The
PWM remap mode uses two EPA channels to eliminate this problem.
5.6.6.2
PWM Remap Mode Example
Figure 5-18 shows the PTS control block for PWM remap mode. The following example uses two
EPA channels and a single timer to generate a PWM waveform in PWM remap mode. EPA0 as-
serts the output, and EPA1 deasserts it. For each channel, an interrupt is generated every T2 pe-
riod, but the comparison times for the channels are offset by the on-time, T1 (see Figure 5-15 on
page 5-32). Although TBIT is toggled at the end of every PWM remap mode cycle (see Table
5-12 on page 5-32), it plays no role in this mode. To generate a PWM waveform, follow this pro-
cedure.
1.
Disable the interrupts and the PTS. The DI instruction disables all interrupts; the DPTS
instruction disables the PTS.
2.
Set up one PTSCB for EPA0 and one for EPA1 as shown in Table 5-14. Note that the two
blocks are identical, except that PTSPTR1 points to EPA0_TIME for EPA0 and to
EPA1_TIME for EPA1.
3.
Configure P1.1 to serve as the EPA1 output. (Because EPA0 is not used as an output, port
pin P1.0 can be used for standard I/O.)
— Clear P1_DIR.1 (selects output)
— Set P1_MODE.1 (selects the EPA0 special-function signal)
— Set P1_REG.1 (initializes the output to “1”)
Summary of Contents for 8XC196NT
Page 1: ...8XC196NT Microcontroller User s Manual...
Page 2: ...8XC196NT Microcontroller User s Manual June 1995 Order Number 272317 003...
Page 22: ...1 Guide to This Manual...
Page 23: ......
Page 35: ......
Page 36: ...2 Architectural Overview...
Page 37: ......
Page 49: ......
Page 50: ...3 Programming Considerations...
Page 51: ......
Page 66: ...4 Memory Partitions...
Page 67: ......
Page 104: ...5 Standard and PTS Interrupts...
Page 105: ......
Page 147: ......
Page 148: ...6 I O Ports...
Page 149: ......
Page 176: ...7 Serial I O SIO Port...
Page 177: ......
Page 194: ...8 Synchronous Serial I O SSIO Port...
Page 195: ......
Page 211: ......
Page 212: ...9 Slave Port...
Page 213: ......
Page 231: ......
Page 232: ...10 Event Processor Array EPA...
Page 233: ......
Page 270: ...11 Analog to digital Converter...
Page 271: ......
Page 291: ......
Page 292: ...12 Minimum Hardware Considerations...
Page 293: ......
Page 306: ...13 Special Operating Modes...
Page 307: ......
Page 317: ......
Page 318: ...14 Interfacing with External Memory...
Page 319: ......
Page 362: ...15 Programming the Nonvolatile Memory...
Page 363: ......
Page 408: ...A Instruction Set Reference...
Page 409: ......
Page 476: ...B Signal Descriptions...
Page 477: ......
Page 493: ......
Page 494: ...C Registers...
Page 495: ......
Page 565: ......
Page 566: ...Glossary...
Page 567: ......
Page 580: ...Index...
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Page 597: ......