Intel 8XC196NT, User Manual

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8-5
SYNCHRONOUS SERIAL I/O (SSIO) PORT
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The two channels can operate together, from the same clock, as master transceivers to
communicate in lockstep (mutually synchronous), full-duplex mode. This mode requires
one data input pin, one data output pin, and two clock pins (the clock output pin from one
channel connected to the clock input pin of the other).
•
The two channels can operate together, from the same clock, as slave transceivers to
communicate in lockstep (mutually synchronous), full-duplex mode. This mode requires
one data input pin, one data output pin, and two clock input pins.
•
The two channels can operate independently, with different clocks, to communicate in non-
lockstep, full-duplex mode. In this mode, one channel acts as slave (receives a clock) and
the other acts as master (transmits a clock). This mode requires a data input pin, a data
output pin, a clock input pin, and a clock output pin.
The SSIO channels can also operate in handshaking modes for unidirectional, multi-byte trans-
fers. These modes enable a master device to perform SSIO transfers using the PTS. Handshaking
prevents a data underflow or overflow from occurring at the slave. It takes place in hardware, us-
ing the clock pins, with no CPU overhead.
•
The two channels can operate with handshaking enabled, in full-duplex mode. One channel
acts as slave and the other acts as master. This mode requires four pins.
•
The two channels can operate with handshaking enabled, in half-duplex mode. One channel
acts as slave and the other acts as master. This mode requires two pins.
Each channel contains an 8-bit buffer register, SSIOx_BUF, and logic to clock the data into and
out of the transceiver. In receive mode, data is shifted (MSB first) from the SDx pin into
SSIOx_BUF. In transmit mode, data is shifted from SSIOx_BUF onto the SDx pin. The receiver
latches data from the transmitter on the rising edge of SCx and the transmitter changes (or floats)
output data on the falling edge of SCx.
In the handshaking modes, the clock polarities are reversed, so the corresponding clock edges are
also reversed. The clock pin, SCx, must be configured as an open-drain output in both master and
slave modes. (This configuration requires an external pull-up.) The master leaves the SCx output
high at the end of each byte transfer. The slave pulls its clock input low when it is busy. (In receive
mode, the slave is busy when the buffer is full; in transmit mode, the slave is busy when the buffer
is empty.) The slave releases SCx when it is ready to receive or transmit. The master waits for
SCx to return high before attempting the next transfer. Figure 8-3 illustrates transmit and receive
timings with and without handshaking.