Intel 8XC196NT, User Manual

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8XC196NT USER’S MANUAL
B-8
INTOUT# O Interrupt Output
This active-low output indicates that a pending interrupt requires use of the
external bus. How quickly the 8XC196NT
asserts INTOUT# depends upon the
status of HOLD# and HLDA# and whether the device is executing from internal
or external program memory. If the 8XC196NT receives an interrupt request
while it is in hold and it is executing code from internal memory, it asserts
INTOUT# immediately. However, if the 8XC196NT is executing code from
external memory, it asserts BREQ# and waits until the external device
deasserts HOLD# to assert INTOUT#. If the 8XC196NT is executing code from
external memory and it receives an interrupt request as it is going into hold
(between the time that an external device asserts HOLD# and the time that the
8XC196NT responds with HLDA#), the 8XC196NT asserts both HLDA# and
INTOUT# and keeps them asserted until the external device deasserts HOLD#.
INTOUT is multiplexed with P2.4 and AINC#.
NMI I Nonmaskable Interrupt
In normal operating mode, a rising edge on NMI causes a vector through the
NMI interrupt at location FF203EH. NMI must be asserted for greater than one
state time to guarantee that it is recognized.
In idle mode, a rising edge on the NMI pin causes the device to return to normal
operation, where the first action is to execute the NMI service routine. After
completion of the service routine, execution resumes at the instruction following
the IDLPD instruction that put the device into idle mode.
In powerdown mode, a rising edge on the NMI pin does not cause the device to
exit powerdown.
ONCE# I On-circuit Emulation
Holding ONCE# low during the rising edge of RESET# places the device into
on-circuit emulation (ONCE) mode. This mode puts all pins into a high-
impedance state, thereby isolating the device from other components in the
system. The value of ONCE# is latched when the RESET# pin goes inactive.
While the device is in ONCE mode, you can debug the system using a clip-on
emulator. To exit ONCE mode, reset the device by pulling the RESET# signal
low. To prevent inadvertent entry into ONCE mode, either configure this pin as
an output or hold it high during reset and ensure that your system meets the V
IH
specification (see datasheet).
ONCE# is multiplexed with P2.6.
P0.7:4 I Port 0
This is a high-impedance, input-only port. Port 0 pins should not be left floating.
These pins may individually be used as analog inputs (ACH x ) or digital inputs
(P0.
x
). While it is possible for the pins to function simultaneously as analog and
digital inputs, this is not recommended because reading port 0 while a
conversion is in process can produce unreliable conversion results.
ANGND and V
REF
must be connected for port 0 to function.
P0.7:4 are multiplexed with ACH7:4 and PMODE.3:0.
P1.7:0 I/O Port 1
This is a standard, bidirectional port that is multiplexed with individually
selectable special-function signals.
Port 1 is multiplexed as follows: P1.0/EPA0, P1.1/EPA1, P1.2/EPA2,
P1.3/EPA3, P1.4/T1CLK, P1.5/T1DIR, P1.6/T2CLK, and P1.7/T2DIR.
Table B-4. Signal Descriptions (Continued)
Name Type Description