![Intel 8XC196NT User Manual Download Page 382](http://html1.mh-extra.com/html/intel/8xc196nt/8xc196nt_user-manual_2072210382.webp)
15-19
PROGRAMMING THE NONVOLATILE MEMORY
15.8.4 Slave Programming Routines
The slave programming mode algorithm consists of three routines: the address/command decod-
ing routine, the program word routine, and the dump word routine.
The address/command decoding routine (Figure 15-7) reads the PBUS and transfers control to
the program word or dump word routine based on the value of P3.0. A one on P3.0 selects the
program word command and the remaining bits specify the address. For example, a PBUS value
of 3501H programs a word of data at location 3500H. A zero on P3.0 selects the dump word com-
mand and the remaining bits specify the address. For example, a PBUS value of 3500H places
the word at location 3500H on the PBUS.
The program word routine (Figure 15-8) checks the CCB security-lock bits. If either security lock
bit (CCB0.6 or CCB0.7) has been programmed, you must provide a matching security key to gain
access to the device. Using the program word command, write eight consecutive words to the de-
vice, starting at location 2020H and continuing to 202FH. The routine stores these eight words in
an internal register and compares their value with the internal key. If the keys match, the routine
allows you to program individual or sequential OTPROM locations; otherwise, the device enters
an endless loop.
The dump word routine (Figure 15-10) also checks the CCB security-lock bits, but it has no pro-
vision for security key verification. If the lock bits are unprogrammed, the routine fetches a word
of data from the OTPROM and writes that data to the PBUS. If either lock bit is programmed, the
routine performs a write cycle without first getting data from the OTPROM.
Summary of Contents for 8XC196NT
Page 1: ...8XC196NT Microcontroller User s Manual...
Page 2: ...8XC196NT Microcontroller User s Manual June 1995 Order Number 272317 003...
Page 22: ...1 Guide to This Manual...
Page 23: ......
Page 35: ......
Page 36: ...2 Architectural Overview...
Page 37: ......
Page 49: ......
Page 50: ...3 Programming Considerations...
Page 51: ......
Page 66: ...4 Memory Partitions...
Page 67: ......
Page 104: ...5 Standard and PTS Interrupts...
Page 105: ......
Page 147: ......
Page 148: ...6 I O Ports...
Page 149: ......
Page 176: ...7 Serial I O SIO Port...
Page 177: ......
Page 194: ...8 Synchronous Serial I O SSIO Port...
Page 195: ......
Page 211: ......
Page 212: ...9 Slave Port...
Page 213: ......
Page 231: ......
Page 232: ...10 Event Processor Array EPA...
Page 233: ......
Page 270: ...11 Analog to digital Converter...
Page 271: ......
Page 291: ......
Page 292: ...12 Minimum Hardware Considerations...
Page 293: ......
Page 306: ...13 Special Operating Modes...
Page 307: ......
Page 317: ......
Page 318: ...14 Interfacing with External Memory...
Page 319: ......
Page 362: ...15 Programming the Nonvolatile Memory...
Page 363: ......
Page 408: ...A Instruction Set Reference...
Page 409: ......
Page 476: ...B Signal Descriptions...
Page 477: ......
Page 493: ......
Page 494: ...C Registers...
Page 495: ......
Page 565: ......
Page 566: ...Glossary...
Page 567: ......
Page 580: ...Index...
Page 581: ......
Page 597: ......