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Intel 8XC196NT, User Manual

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8XC196NT USER’S MANUAL

15-10

Figure 15-3.  Modified Quick-pulse Algorithm 

Auto programming repeats the pulse five times, using the pulse width you specify in the external
EPROM. Slave mode repeats the pulse until PROG# is deasserted. In slave programming mode,
the PALE# signal controls the pulse width. In all cases, the pulse width must be at least 100 µs
for successful programming. 

A0190-03

Return

From Auto or Slave

Programming

Required

Writes Done

?

Start PPW Timer

Write Data to

OTPROM

Enter Idle Mode

Wait for PPW Timer Interrupt

Yes

No

Enable Interrupts

Compare Programmed

Locations and Set Flags

           

Summary of Contents for 8XC196NT

Page 1: ...8XC196NT Microcontroller User s Manual...

Page 2: ...8XC196NT Microcontroller User s Manual June 1995 Order Number 272317 003...

Page 3: ...ns the right to make changes to these specifications at any time without notice Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your produc...

Page 4: ...CHAPTER 2 ARCHITECTURAL OVERVIEW 2 1 TYPICAL APPLICATIONS 2 1 2 2 DEVICE FEATURES 2 1 2 3 BLOCK DIAGRAM 2 1 2 3 1 CPU Control 2 3 2 3 2 Register File 2 3 2 3 3 Register Arithmetic logic Unit RALU 2 3...

Page 5: ...ect Addressing 3 8 3 2 3 2 Indirect Addressing with Autoincrement 3 8 3 2 3 3 Extended Indirect Addressing with Autoincrement 3 8 3 2 3 4 Indirect Addressing with the Stack Pointer 3 9 3 2 4 Indexed A...

Page 6: ...Window 4 17 4 3 2 1 32 byte Windowing Example 4 19 4 3 2 2 64 byte Windowing Example 4 19 4 3 2 3 128 byte Windowing Example 4 19 4 3 2 4 Unsupported Locations Windowing Example 4 20 4 3 2 5 Using the...

Page 7: ...5 5 2 Modifying Interrupt Priorities 5 14 5 5 3 Determining the Source of an Interrupt 5 16 5 5 3 1 Determining the Source of Multiplexed Interrupts 5 16 5 6 INITIALIZING THE PTS CONTROL BLOCKS 5 18 5...

Page 8: ...tions 6 25 6 5 3 1 EPORT Status During Reset CCB Fetch Idle Powerdown and Hold 6 25 6 5 3 2 EP_REG Settings for Pins Configured as Extended address Signals 6 25 6 5 3 3 EPORT Status During Instruction...

Page 9: ...T 9 1 SLAVE PORT FUNCTIONAL OVERVIEW 9 2 9 2 SLAVE PORT SIGNALS AND REGISTERS 9 2 9 3 HARDWARE CONNECTIONS 9 6 9 4 SLAVE PORT MODES 9 8 9 4 1 Standard Slave Mode Example 9 8 9 4 1 1 Master Device Prog...

Page 10: ...pt Service Overhead 10 31 10 9 PROGRAMMING EXAMPLES FOR EPA CHANNELS 10 33 10 9 1 EPA Compare Event Program 10 33 10 9 2 EPA Capture Event Program 10 34 10 9 3 EPA PWM Output Program 10 35 CHAPTER 11...

Page 11: ...2 CHAPTER 13 SPECIAL OPERATING MODES 13 1 SPECIAL OPERATING MODE SIGNALS AND REGISTERS 13 1 13 2 REDUCING POWER CONSUMPTION 13 3 13 3 IDLE MODE 13 3 13 4 POWERDOWN MODE 13 4 13 4 1 Enabling and Disabl...

Page 12: ...PROGRAMMING THE NONVOLATILE MEMORY 15 1 PROGRAMMING METHODS 15 1 15 2 OTPROM MEMORY MAP 15 2 15 3 SECURITY FEATURES 15 3 15 3 1 Controlling Access to Internal Memory 15 3 15 3 1 1 Controlling Access t...

Page 13: ...rom Internal RAM 15 34 15 10 4 Reduced Instruction Set Monitor RISM 15 34 15 10 5 RISM Command Descriptions 15 35 15 10 6 RISM Command Examples 15 37 15 10 6 1 Example 1 Programming the PPW 15 37 15 1...

Page 14: ...5 Interrupt Mask INT_MASK Register 5 13 5 6 Interrupt Mask 1 INT_MASK1 Register 5 14 5 7 Interrupt Pending INT_PEND Register 5 17 5 8 Interrupt Pending 1 INT_PEND1 Register 5 18 5 9 PTS Control Block...

Page 15: ...Quadrature Mode Interface 10 8 10 4 Quadrature Mode Timing and Count 10 9 10 5 A Single EPA Capture Compare Channel 10 10 10 6 EPA Simplified Input capture Structure 10 11 10 7 Valid EPA Input Events...

Page 16: ...plexing and Bus Width Options 14 11 14 5 BUSWIDTH Timing Diagram 14 12 14 6 Timings for 16 bit Buses 14 14 14 7 Timings for 8 bit Buses 14 16 14 8 READY Timing Diagram 14 19 14 9 HOLD HLDA Timing 14 2...

Page 17: ...oding Routine 15 20 15 8 Program Word Routine 15 21 15 9 Program Word Waveform 15 22 15 10 Dump Word Routine 15 23 15 11 Dump Word Waveform 15 24 15 12 Auto Programming Circuit 15 26 15 13 Auto Progra...

Page 18: ...4 4 9 Selecting a Window of 8XC196NT Peripheral SFRs 4 16 4 10 Selecting a Window of the Upper Register File 4 17 4 11 Windows 4 18 4 12 Windowed Base Addresses 4 19 4 13 Memory Access for the 87C196N...

Page 19: ...7 2 7 3 SP_BAUD Values When Using XTAL1 at 20 MHz 7 11 8 1 SSIO Port Signals 8 2 8 2 SSIO Port Control and Status Registers 8 2 8 3 Common SSIO_BAUD Values When Using XTAL1 at 20 MHz 8 10 9 1 Slave P...

Page 20: ...lags A 4 A 3 Effect of PSW Flags or Specified Bits on Conditional Jump Instructions A 5 A 4 PSW Flag Setting Symbols A 5 A 5 Operand Variables A 6 A 6 Instruction Set A 7 A 7 Instruction Opcodes A 46...

Page 21: ...on SSIO_BAUD Values When Using XTAL1 at 20 MHz C 57 C 14 SSIOx_BUF Addresses and Reset Values C 58 C 15 SSIOx_CON Addresses and Reset Values C 60 C 16 TIMERx Addresses and Reset Values C 63 C 17 WSR S...

Page 22: ...1 Guide to This Manual...

Page 23: ......

Page 24: ...ware It de scribes the core internal timing internal peripherals and special operating modes Chapter 3 Programming Considerations provides an overview of the instruction set de scribes general standar...

Page 25: ...options Chapter 13 Special Operating Modes provides an overview of the idle powerdown and on circuit emulation ONCE modes and describes how to enter and exit each mode Chapter 14 Interfacing with Ext...

Page 26: ...as FFFFFFH while the highest possible external address is shown as FFFFFH When writing code use the appropriate address conventions for the software tool you are using For assembly code a zero must p...

Page 27: ...resented by the register name followed by a period and the bit number For example WSR 7 is bit 7 of the window selection register In some discussions bit names are used Register Names Register mnemoni...

Page 28: ...ry indicates that the two LSBs are unknown 1 3 RELATED DOCUMENTS The tables in this section list additional documents that you may find useful in designing systems incorporating MCS 96 microcontroller...

Page 29: ...icrocontrollers Data sheets and architecture descriptions for Intel s three industry standard microcontrollers the MCS 48 MCS 51 and MCS 96 microcontrollers 270646 Peripheral Components Comprehensive...

Page 30: ...7 Included in Embedded Microcontrollers handbook order number 270646 Table 1 4 MCS 96 Microcontroller Datasheets Automotive Title and Description Order Number 87C196CA 87C196CB 20 MHz Advanced 16 Bit...

Page 31: ...pe Think of the FaxBack service as a library of technical documents that you can access with your phone Just dial the telephone number and respond to the system prompts After you select a doc ument th...

Page 32: ...odems Typical modem settings are 14400 baud no parity 8 data bits and 1 stop bit 14400 N 8 1 To access the BBS just dial the telephone number and respond to the system prompts During your first sessio...

Page 33: ...ons one for ApBUILDER software and the others for hypertext documents for specific product families 4 Type 1 and press Enter to list the latest ApBUILDER files or type 2 and press Enter to list the hy...

Page 34: ...l distributor 1 800 628 8686 U S and Canada 916 356 7599 U S and Canada 916 356 6100 fax U S and Canada 1 6 PRODUCT LITERATURE You can order product literature from the following Intel literature cent...

Page 35: ......

Page 36: ...2 Architectural Overview...

Page 37: ......

Page 38: ...features of the 8XC196NT 2 3 BLOCK DIAGRAM Figure 2 1 shows the major blocks within the device The core of the device Figure 2 2 consists of the central processing unit CPU and memory controller The...

Page 39: ...apter 6 I O Ports for additional information Figure 2 1 8XC196NT Block Diagram Figure 2 2 Block Diagram of the Core A2800 01 Optional ROM Core Code Data RAM Clock and Power Mgmt PTS SSIO EPA I O A D S...

Page 40: ...abled Windowing is a technique that maps blocks of the upper register file into a window in the lower register file See Chapter 4 Memory Partitions for more information about the register file and win...

Page 41: ...tants register generates single bit masks based on the bit select reg ister for bit test instructions 2 3 3 1 Code Execution The RALU performs most calculations for the device but it does not use an a...

Page 42: ...yte is available immediately and the processor need not wait for the master PC to send the ad dress to the memory controller If a jump interrupt call or return changes the address sequence the master...

Page 43: ...erlapping internal timing signals PH1 and PH2 These signals are active when high The rising edges of PH1 and PH2 gen erate CLKOUT the output of the internal clock generator Figure 2 4 The clock circui...

Page 44: ...defines time requirements in terms of state times rather than specific times Consult the latest datasheet for AC timing specifi cations 2 5 INTERNAL PERIPHERALS The internal peripheral modules provid...

Page 45: ...direct addresses they cannot be windowed Ports 3 and 4 serve as the 16 bit external address data bus Port 3 can also serve as the slave port to provide an interface between two 8XC196NT family devices...

Page 46: ...DPRAM on chip With this configuration an external master processor can simply read from and write to the on chip memory of the 8XC196 slave device The slave port requires more pins than a serial link...

Page 47: ...device if the software fails to operate properly See Chapter 12 Minimum Hardware Considerations for more information 2 6 SPECIAL OPERATING MODES In addition to the normal execution mode the device op...

Page 48: ...ete Serial port programming allows you to download code and data usually from a personal computer or workstation to an MCS 96 microcontroller asynchronously through the serial I O port s RXD and TXD p...

Page 49: ......

Page 50: ...3 Programming Considerations...

Page 51: ......

Page 52: ...Yes 27 through 27 1 128 through 127 None WORD 16 No 0 through 216 1 0 through 65 535 Even byte address INTEGER 16 Yes 215 through 215 1 32 768 through 32 767 Even byte address DOUBLE WORD Note 1 32 N...

Page 53: ...e least significant bit There are no alignment restric tions for BYTEs so they may be placed anywhere in the address space 3 1 3 SHORT INTEGER Operands A SHORT INTEGER is an 8 bit signed variable that...

Page 54: ...least significant byte of the INTEGER is in the even byte address and the most significant byte is in the next high er odd address The address of an INTEGER is that of its least significant byte the e...

Page 55: ...the operand of the EB MOVI instruction For this operation the QUAD WORD variable must reside in the lower reg ister file and must be aligned at an address that is evenly divisible by eight 3 1 9 Conv...

Page 56: ...EBMOVI Extended interruptable block move Moves a block of word data from one memory location to another This instruction allows you to move blocks of up to 64K words between any two locations in the a...

Page 57: ...ed with long indexed addressing to access any memory location Extended variations of the indirect and indexed modes support the extended load and store in structions An extended load instruction moves...

Page 58: ...se immediate addressing ADD AX 340 AX AX 340 PUSH 1234H SP SP 2 MEM_WORD SP 1234H DIVB AX 10 AL AX 10 AH AX MOD 10 3 2 3 Indirect Addressing The indirect addressing mode accesses an operand by obtaini...

Page 59: ...automatically increments the indirect address by one if the destination is an 8 bit register or by two if it is a 16 bit register When your code is assembled the assembler automat ically sets the leas...

Page 60: ...ant and the base address as an indirect address register a WORD The following instructions use short indexed addressing LD AX 12 BX AX MEM_WORD BX 12 MULB AX BL 3 CX AX BL MEM_BYTE CX 3 The instructio...

Page 61: ...tended in dexed addressing In these instructions OFFSET is a 24 bit variable containing the offset and EX is a double word aligned 24 bit register containing the base address ELD AX OFFSET EX AX MEM_W...

Page 62: ...page 00H then you must use the extended load and store instructions ELD ELDB EST and ESTB 3 4 DESIGN CONSIDERATIONS FOR 1 MBYTE DEVICES In general you should avoid creating tables or arrays that cros...

Page 63: ...base or index register for indirect or indexed operations can cause unpredictable results External events can change the contents of SFRs and some SFRs are cleared when read For this reason consider...

Page 64: ...d calling convention adopted by the C programming language has several key fea tures Procedures can always assume that the eight or sixteen bytes of register file memory starting at 1CH can be used as...

Page 65: ...on This is particularly important in the code surrounding lookup tables since accidentally executing from lookup tables will cause undesired results Wherever space allows surround each table with seve...

Page 66: ...4 Memory Partitions...

Page 67: ......

Page 68: ...ng examples of external memory configurations for the 1 Mbyte and 64 Kbyte modes a method for remapping the 32 Kbyte internal OTPROM 87C196NT only 4 1 MEMORY MAP OVERVIEW The instructions can address...

Page 69: ...ains special purpose memory chip configuration bytes and in terrupt vectors and program memory The device fetches its first instruction from location FF2080H Addresses in page FFH exist only in the in...

Page 70: ...0100H FF00FFH FF0000H 00FFFFH 00A000H 009FFFH 002000H 001FFFH 001FE0H 001FDFH 001F00H 001EFFH 000600H 0005FFH 000400H 0003FFH 000100H 0000FFH 000000H External Memory A3055 02 Page 00H Memory mapped SF...

Page 71: ...001FFF 001FE0 Memory mapped SFRs Indirect indexed extended 001FDF 001F00 Peripheral SFRs Indirect indexed extended windowed direct 001EFF 000600 External device memory or I O connected to address dat...

Page 72: ...FF2000 FF9FFFH For the 80C196NT this partition resides in external memory ex ternal addresses F2000 F9FFFH For the 87C196NT this partition can reside either in external memory external addresses F2000...

Page 73: ...2 2 the EA input and the type of instruction extended or nonextended control access to this partition as shown in Table 4 3 Table 4 2 Program Memory Access for the 87C196NT REMAP CCB2 2 EA Instruction...

Page 74: ...See Chapter 5 Standard and PTS Interrupts for more information on interrupt and PTS vectors 4 2 2 5 Security Key The security key prevents unauthorized programming access to the OTPROM See Chapter 15...

Page 75: ...14 5 de scribes the CCBs and CCRs 4 2 3 Special function Registers SFRs The 8XC196NT has both peripheral SFRs and memory mapped SFRs The peripheral SFRs are physically located in the on chip peripher...

Page 76: ...ther as words or bytes except as noted in the table Table 4 5 8XC196NT Memory mapped SFRs Ports 3 4 5 Slave Port UPROM SFRs EPORT and Internal RAM SFRs Hex Address High Odd Byte Low Even Byte Hex Addr...

Page 77: ...erved Reserved 1F84H Reserved EPA9_CON SIO and SSIO SFRs 1F82H EPA8_TIME H EPA8_TIME L Address High Odd Byte Low Even Byte 1F80H Reserved EPA8_CON 1FBEH Reserved Reserved 1F7EH EPA7_TIME H EPA7_TIME L...

Page 78: ...N Address Reset State 1FE0H 00H The internal RAM control IRAM_CON register has two functions related to memory accesses The IRAM bit allows you to control access to locations 0400 05FFH The EA_STAT bi...

Page 79: ...memory controller It also accesses a windowed loca tion directly see Windowing on page 4 15 Only the upper register file and the peripheral SFRs can be windowed Registers in the lower register file a...

Page 80: ...two bytes for 64 Kbyte mode or four bytes for 1 Mbyte mode greater than the desired starting address Before the CPU exe cutes a subroutine call or interrupt service routine it decrements the SP by tw...

Page 81: ...e first byte of the return address onto the stack Remember that the stack grows downward so allow sufficient room for the maximum number of stack entries The stack must be located in page 00H in eithe...

Page 82: ...ctions With window ing direct addressing can also access the upper register file and peripheral SFRs NOTE Memory mapped SFRs must be accessed using indirect or indexed addressing modes they cannot be...

Page 83: ...32 64 or 128 byte increments PUSHA saves this register on the stack and POPA restores it 7 0 HLDEN W6 W5 W4 W3 W2 W1 W0 Bit Number Bit Mnemonic Function 7 HLDEN HOLD HLDA Protocol Enable This bit ena...

Page 84: ...ffset to the base address of the window from Table 4 12 on page 4 19 The result is the direct address Table 4 10 Selecting a Window of the Upper Register File Register RAM Locations Hex WSR Value for...

Page 85: ...egister File 03E0H 5FH 2FH 17H 03C0H 5EH 03A0H 5DH 2EH 0380H 5CH 0360H 5BH 2DH 16H 0340H 5AH 0320H 59H 2CH 0300H 58H 02E0H 57H 2BH 15H 02C0H 56H 02A0H 55H 2AH 0280H 54H 0260H 53H 29H 14H 0240H 52H 022...

Page 86: ...wish to access the SFR at location 1F8CH with direct addressing through a 64 byte window Table 4 11 on page 4 18 shows that you need to write 3EH to the window selection register It also shows that th...

Page 87: ...FDFH 4 3 2 5 Using the Linker Locator to Set Up a Window In this example the linker locator is used to set up a window The linker locator locates the win dow in the upper register file and determines...

Page 88: ...the proper windowing RL196 MOD1 OBJ MOD2 OBJ registers 100h 03ffh windowsize 32 The above linker controls tell the linker to use registers 0100 03FFH for windowing and to use a window size of 32 bytes...

Page 89: ...rect or indexed operations To re enable direct access to the entire lower register file clear the WSR To enable direct access to a particular location in the lower register file you may select a small...

Page 90: ...F2000 F9FFFH when EA is low In either case data in this area must be accessed with extended instructions With remapping enabled CCB2 2 1 and EA inactive you can access the contents of FF2000 FF9FFFH...

Page 91: ...e can fetch code from any page in the 1 Mbyte address space 00H 0FH and FFH FFH overlays 0FH In 64 Kbyte mode the EPC is fixed at FFH which limits program memory to page FFH and 0FH Figure 4 7 The 24...

Page 92: ...W 1 CSEG AT 0FF2080H SOME CODE SUBB PUSHA save flags disable interrupts LD TEMP 1234H EST TEMP 010600H store temp value in 010600H ADD RESULT TEMP 4000H do something with registers EST RESULT 010602H...

Page 93: ...device 80C196NT For devices without internal nonvolatile memory EA must be tied low and code executes from any page in external memory 87C196NT Code in all locations except FF2000 FF9FFFH executes fro...

Page 94: ...ad or store instruction executing from any other page accesses external memory For example if code is executing from page 05H the following instructions write to different memory locations stb temp 30...

Page 95: ...face in detail and provides additional examples 4 6 1 Example 1 A 64 Kbyte Mode 87C196NT System Figure 4 9 illustrates a system designed to operate in the 64 Kbyte mode CCB2 1 1 Code ex ecutes only fr...

Page 96: ...T 0 AD15 8 A14 8 A7 0 D7 0 OE AD7 0 ALE RD D7 0 OE WE 74LS373 87C196NT Page 00H 000000 0005FFH 001F00 009FFFH Page FFH FF0400 FF05FFH FF2000 FF9FFFH WR WE VCC A15 8 A7 0 CE Page 00H 32K 8 RAM near dat...

Page 97: ...0 Unimplemented FF9FFF FF2000 Internal OTPROM code and far constants FF1FFF FF0600 Unimplemented FF05FF FF0400 Internal code and data RAM mapped from page 00H FF03FF FF0100 Unimplemented FF00FF FF0000...

Page 98: ...ed See Bus Timing Modes on page 14 34 Table 4 14 lists the memory addresses for this example Figure 4 10 A 64 Kbyte System with Additional Data Storage A3059 02 EA EPORT 0 AD15 8 A15 8 A7 0 D7 0 OE AD...

Page 99: ...Figure 4 10 Address Description FFFFFF FFA000 Unimplemented FF9FFF FF2000 Internal OTPROM code and far constants FF1FFF FF0600 Unimplemented FF05FF FF0400 Internal code and data RAM mapped from page...

Page 100: ...ogic one selects the 64K 16 flash Any of the four bus timing modes can be selected because two address latches are used See Bus Timing Modes on page 14 34 Table 4 14 lists the memory addresses for thi...

Page 101: ...PROM code and far constants FF1FFF FF0600 Unimplemented FF05FF FF0400 Internal code and data RAM mapped from page 00H FF03FF FF0100 Unimplemented FF00FF FF0000 Reserved 0FFFFF 040000 Unimplemented 03F...

Page 102: ...A17 A16 Page 00H 64K 8 Flash near data 00600 01EFFH 02000 0FFFFH A15 8 A7 0 D7 0 OE WE AD7 0 ALE WR RD A7 0 A15 8 A7 0 D7 0 OE WE CE2 Page 0FH 64K 8 Flash code special purpose memory and far data F000...

Page 103: ...exam ple This memory map assumes that the IRAM bit IRAM_CON 6 is set so accesses to FF0400 FF05FFH are directed to the external flash memory Table 4 17 Memory Map for the System in Figure 4 12 Addres...

Page 104: ...5 Standard and PTS Interrupts...

Page 105: ......

Page 106: ...he interrupt controller are serviced by interrupt service routines that you provide The upper and lower interrupt vectors in special purpose memory see Chapter 4 Memory Partitions contain the lower 16...

Page 107: ...MASK x 1 No Return Yes Return Reset INT_PEND x Bit Reset PTSSRV x Bit Priority Encoder Highest Priority Interrupt PUSH PC on Stack LJMP to ISR Execute Interrupt Service Routine POP PC from Stack Prior...

Page 108: ...ction following the one that put the device into idle mode In powerdown mode asserting EXTINT causes the device to return to normal operating mode If EXTINT is enabled the EXTINT service routine is ex...

Page 109: ...n the EPAx interrupt is activated Reading this register clears the pending bit of the associated interrupt source The EPAx pending bit INT_PEND 7 is cleared when all the pending bits for its sources i...

Page 110: ...0 INT09 FF2032H 09 PTS09 FF2052H 24 Slave Port Command Buff Full CBF INT08 FF2030H 08 PTS08 FF2050H 23 Unimplemented Opcode FF2012H Software TRAP Instruction FF2010H Slave Port Input Buff Full IBF INT...

Page 111: ...ests from being acknowledged until after the next instruction is executed 5 3 1 2 Software Trap The TRAP instruction opcode F7H causes an interrupt call that is vectored through location FF2010H The T...

Page 112: ...rupt vectors through FF2056H but the cor responding end of PTS interrupt vectors through FF2036H the standard SIO transmit interrupt vector When the end of PTS interrupt vectors to the interrupt servi...

Page 113: ...ion times 5 4 2 Calculating Latency The maximum latency occurs when the interrupt request occurs too late for acknowledgment fol lowing the current instruction The following worst case calculation ass...

Page 114: ...4 Kbyte and 1 Mbyte modes Figure 5 2 Standard Interrupt Response Time 5 4 2 2 PTS Interrupt Latency In both 64 Kbyte and 1 Mbyte modes the maximum delay for a PTS interrupt is 43 state times 4 39 Figu...

Page 115: ...register memory register memory memory 18 per byte or word transfer 1 21 per byte or word transfer 1 24 per byte or word transfer 1 Block transfer mode register register memory register memory memory...

Page 116: ...ter a DI disable interrupts instruction if the appropriate INT_MASK and PTSSEL bits are set However the end of PTS interrupt request will not be serviced If an interrupt request occurs while interrupt...

Page 117: ...it 14 12 0 Setting a bit causes the corresponding interrupt to be handled by a PTS microcode routine The PTS interrupt vector locations are as follows Bit Mnemonic Interrupt PTS Vector EXTINT EXTINT p...

Page 118: ...andard Vector IBF Slave Port Input Buffer Full FF200EH OBE Slave Port Output Buffer Empty FF200CH AD A D Conversion Complete FF200AH EPA0 EPA Capture Compare Channel 0 FF2008H EPA1 EPA Capture Compare...

Page 119: ...dual interrupt requests The EI and DI instructions enable and disable servicing of all maskable interrupts INT_MASK1 can be read from or written to as a byte register PUSHA saves this register on the...

Page 120: ...her interrupt call until after the first instruction of the interrupt service routine is executed 2 The PUSHA instruction which is now guaranteed to execute saves the contents of the PSW INT_MASK INT_...

Page 121: ...They can also be modified written either to clear pending interrupts or to generate interrupts under software control However we recommend the use of the read modify write instructions such as AND and...

Page 122: ...tor locations are as follows Bit Mnemonic Interrupt Standard Vector IBF Slave Port Input Buffer Full FF200EH OBE Slave Port Output Buffer Empty FF200CH AD A D Conversion Complete FF200AH EPA0 EPA Capt...

Page 123: ...ion on page 05 while PTSDST points to page 00 Both PTSSRC and PTSDST will operate from the page defined by EP_REG Write 00H to EP_REG to select page 00H see Accessing Data on page 4 24 INT_PEND1 Addre...

Page 124: ...ests an end of PTS interrupt The end of PTS interrupt service rou tine should reinitialize the PTSCB if required and set the appropriate PTSSEL bit to re enable PTS interrupt service Single Transfer B...

Page 125: ...le the PTS channel 15 8 EXTINT RI TI SSIO1 SSIO0 CBF 7 0 IBF OBE AD EPA0 EPA1 EPA2 EPA3 EPAx Bit Number Function 15 13 Reserved This bit is undefined 14 12 0 A bit is set by hardware to request an end...

Page 126: ...A User s Point of View for application examples with code Figure 5 12 shows the PTS control block for single transfer mode PTSCON Address PTSPCB 1 The PTS control PTSCON register selects the PTS mode...

Page 127: ...Source Address low byte 7 0 PTSCON M2 M1 M0 BW SU DU SI DI 7 0 PTSCOUNT Consecutive Byte or Word Transfers Register Location Function PTSDST PTSCB 4 PTS Destination Address Write the destination memo...

Page 128: ...ess after each byte or word transfer DU Update PTSDST 0 reload original PTS destination address after each byte or word transfer 1 retain current PTS destination address after each byte or word transf...

Page 129: ...location to another using an 8 bit bus with no wait states See Table 5 4 on page 5 10 for execution times of PTS cycles The PTSCB in Table 5 6 sets up three PTS cycles that will transfer five bytes f...

Page 130: ...M0 BW SU DU SI DI 7 0 PTSCOUNT Consecutive Block Transfers Register Location Function PTSBLOCK PTSCB 6 PTS Block Size Specifies the number of bytes or words in each block Valid values are 1 32 inclus...

Page 131: ...omplete DU Update PTSDST 0 reload original PTS destination address after each block transfer is complete 1 retain current PTS destination address after each block transfer is complete SI PTSSRC Autoin...

Page 132: ...R2 L Pointer 2 Value low byte 15 8 PTSPTR1 H Pointer 1 Value high byte 7 0 PTSPTR1 L Pointer 1 Value low byte 7 0 PTSCON M2 M1 M0 0 UPDT 0 1 0 7 0 PTSCOUNT Consecutive A D Conversions Register Locatio...

Page 133: ...he PTSSEL register which disables PTS service and sets the PTSSRV bit which requests an end of PTS interrupt The interrupt service routine could process the conversion results and then re enable PTS s...

Page 134: ...data If UPDT is set the updated address remains in PTSPTR1 and the next cycle uses a new command and stores the conversion results at the new address 5 PTSCOUNT is decremented and the CPU returns to...

Page 135: ...esult in a single location 3002H The UPDT bit PTSCON 3 is cleared so that original con tents of PTSPTR1 are restored after the cycle The command data table is shown in Table 5 10 Table 5 8 Command Dat...

Page 136: ...ts of the first cycle The value of the AD_RESULT register is written to location 3002H and the command at location 3000H is re executed 5 6 6 PWM Modes The PWM toggle and PWM remap modes are designed...

Page 137: ...interrupt and reconfigure the EPA channel in the interrupt service routine Table 5 12 Comparison of PWM Modes PWM Toggle Mode PWM Remap Mode Uses a single EPA channel Uses two EPA channels Reads the l...

Page 138: ...nitial TBIT value 1 Set up PTSPTR1 to point to EPA0_TIME the EPA0 event time register Load PTSCONST1 with the on time T1 from CSTORE1 Load PTSCONST2 with the off time T2 T1 from CSTORE2 5 Configure P1...

Page 139: ...nd a control register PTSCON 7 0 PTSCONST2 H PWM Off time high byte 7 0 PTSCONST2 L PWM Off time low byte 15 8 PTSCONST1 H PWM On time high byte 7 0 PTSCONST1 L PWM On time low byte 15 8 PTSPTR1 H Poi...

Page 140: ...toggles the TBIT to one The next timer match occurs at t T2 T1 The EPA toggles the output to zero and initiates the third PTS cycle The PTS actions are the same as in cycle 1 and generation of the PW...

Page 141: ...atch occurs the out put is toggled and the device executes a normal interrupt service routine which performs these operations 1 The routine writes the new value of T1 in CSTORE1 to PTSCONST1 and the n...

Page 142: ...te a PWM waveform in PWM remap mode EPA0 as serts the output and EPA1 deasserts it For each channel an interrupt is generated every T2 pe riod but the comparison times for the channels are offset by t...

Page 143: ...ables timer 1 selects up counting at FOSC 4 and enables the divide by four prescaler 5 Enable the EPA0 and EPA1 interrupts and select PTS service for them Set INT_MASK 4 and INT_MASK 3 Set PTSSEL 4 an...

Page 144: ...0 0 0 0 0 15 8 PTSCONST1 HI PWM Const 1 Value high byte 7 0 PTSCONST1 LO PWM Const 1 Value low byte 15 8 PTSPTR1 HI Pointer 1 Value high byte 7 0 PTSPTR1 LO Pointer 1 Value low byte 7 0 PTSCON M2 M1 M...

Page 145: ...errupts continue with EPA0 asserting the output and EPA1 deas serting it Register Location Function PTSCON PTSCB 1 PTS Control Bits M2 0 PTS Mode These bits specify the PTS mode M2 M1 M0 0 1 0 PWM TMO...

Page 146: ...1_TIME and set PTSSEL 3 to re enable PTS service for EPA1 This adjustment changes the duty cycle without affecting the period By using two EPA channels in the PWM remap mode you can generate duty cycl...

Page 147: ......

Page 148: ...6 I O Ports...

Page 149: ......

Page 150: ...he pins The chapters that cover the associated peripherals discuss using the pins for their special functions 6 2 INPUT ONLY PORT 0 Port 0 is a four bit high impedance input only port Its pins can be...

Page 151: ...erts the in put signals to work with the VCC and VSS digital voltage levels used by the CPU core This buffer is Schmitt triggered for improved noise immunity The signals are latched in the P0_PIN regi...

Page 152: ...o the internal bus To ensure that the value is recognized it must be valid 45 ns before the rising edge of CLKOUT and must remain valid until CLKOUT falls If the pin value changes during the sam ple t...

Page 153: ...PA6 I O EPA P1 7 EPA7 I O EPA P2 0 TXD O SIO P2 1 RXD I O SIO P2 2 EXTINT I Interrupts P2 3 BREQ O Bus controller P2 4 INTOUT O Interrupts P2 5 HOLD I Bus controller P2 6 HLDA O Bus controller P2 7 CL...

Page 154: ...irectional Open drain outputs require external pull ups P1_MODE P2_MODE P5_MODE P6_MODE 1FD0H 1FC9H 1FF1H 1FD1H Port x Mode Each bit of Px_MODE controls whether the corresponding pin functions as a st...

Page 155: ...uffers for improved noise immunity Port 5 uses a standard input buffer because of the high speeds required for system control functions The signals are latched into the Px_PIN sample latch and output...

Page 156: ...ructure Vcc Q2 Q1 Px_REG Px_DIR Sample Latch PH1 Clock Internal Bus SFDATA SFDIR Px_MODE Px_PIN D Q 0 1 0 1 Vcc Vcc Q R S Any Write to Px_MODE Weak Pullup Medium Pullup RESET RESET Q3 Q4 Vss Read Port...

Page 157: ...Px_PIN contains the current value on the pin 4 During reset and until the first write to Px_MODE Q3 is on Table 6 7 Logic Table for Bidirectional Ports in Special function Mode Configuration Compleme...

Page 158: ...Px_DIR bit Open drain outputs require external pull ups 2 Write to Px_MODE to select either I O or special function mode Writing to Px_MODE regardless of the value written turns off the weak pull ups...

Page 159: ...O Signal Px_DIR Px_MODE Px_REG Complementary output driving 0 0 0 0 Complementary output driving 1 0 0 1 Open drain output strongly driving 0 1 0 0 Open drain output high impedance 1 0 1 Input 1 0 1...

Page 160: ...Figure 6 2 on page 6 7 For this reason even if port 2 is to be used as it is configured at reset you should still write data into P2_MODE P2 2 EXTINT Writing to P2_MODE 2 sets the EXTINT interrupt pe...

Page 161: ...egister not the value in the buffer Therefore any change to P2_REG 7 can be read only after P2_MODE 7 is cleared Port 5 After reset the device configures port 5 to match the external system The follow...

Page 162: ...on of infinite wait states upon the first access to external memory For any other values of IRC0 IRC2 the pin is configured as I O upon reset NOTE If IRC0 IRC2 of the CCB are all set activating READY...

Page 163: ...3 and 4 serve as the programming bus PBUS Port 3 can also serve as the slave port Port 5 supplies the bus control signals During external memory bus cycles the processor takes control of ports 3 and 4...

Page 164: ...ipheral P3 7 0 AD7 0 I O Address data bus low byte PBUS7 0 I O Programming bus low byte SLP7 0 I O Slave port P4 7 0 AD15 8 I O Address data bus high byte PBUS15 8 I O Programming bus high byte Table...

Page 165: ...d Q2 If P34_DRV is set Q1 and Q2 are driven as complementary outputs If P34_DRV is cleared Q1 is disabled and Q2 is driven as an open drain output requiring an external pull up resistor Vcc Q2 Q1 Px_R...

Page 166: ...ing Px_REG bit In comple mentary mode a pin is driven high when the corresponding Px_REG bit is set In open drain mode you need to connect an external pull up resistor When the device requires access...

Page 167: ...bit bidirectional memory mapped I O port This port provides the address signals necessary to support extended addressing It must be accessed using indirect or indexed addressing and it cannot be windo...

Page 168: ...pin as a standard I O port pin EP_PIN 1FE7H EPORT Pin State Each bit of EP_PIN reflects the current state of the corresponding pin regardless of the pin configuration EP_REG 1FE5H EPORT Data Output E...

Page 169: ...e 1 Mbyte mode input and EDAR is loaded with the extended address For nonextended data accesses the data multiplexer is set to the 64 Kbyte mode input and EDAR is loaded from EP_REG The last value loa...

Page 170: ...bled and Q1 and Q2 remain off Otherwise the gates are enabled and complementary or open drain operation is possible 6 5 1 3 Complementary Output Mode For complementary output mode the gates that contr...

Page 171: ...Vcc Q2 Q1 EP_REG EP_MODE Sample Latch PH1 Clock Internal Bus EP_PIN D Q 0 1 Vcc Vcc Weak Pullup Medium Pullup RESET Q3 Q4 Buffer Vss Read Port LE 300ns Delay I O Pin Address Bit from Address MUX EP_DI...

Page 172: ...of EPORT Table 6 16 Logic Table for EPORT in I O Mode Configuration Complementary Output Open drain Output Input EP_MODE 0 0 0 0 EP_DIR 0 0 0 1 Note 2 1 EP_REG 0 1 0 1 Address Bit X X X X Q1 off on o...

Page 173: ...unless you understand the implications of changing memory addressing on the fly To change a pin from I O to address clear the EP_REG x bit and set the EP_MODE x bit Clearing EP_REG x is re quired for...

Page 174: ...access the extended address space However we recommend that you clear the EP_REG bits for any EPORT pins configured as extended address signals in order to maintain compatibility with soft ware devel...

Page 175: ...n the following code example EST 1CH 01001CH 0 reg 1CH stored at memory location 01001CH 6 5 3 4 Design Considerations At the end of EPORT bus activity and during periods of internal bus activity EPOR...

Page 176: ...7 Serial I O SIO Port...

Page 177: ......

Page 178: ...hronous modes modes 1 2 and 3 for both transmission and reception Figure 7 1 SIO Block Diagram The serial port receives data into the receive buffer it transmits data from the port through the transmi...

Page 179: ...he TI bit enables the transmit interrupt clearing the bit disables masks the interrupt Setting the RI bit enables the receive interrupt clearing the bit disables masks the interrupt INT_PEND1 0012H In...

Page 180: ...om the serial port SBUF_TX 1FBAH Serial Port Transmit Buffer This register contains data that is ready for transmission In modes 1 2 and 3 writing to SBUF_TX starts a transmission In mode 0 writing to...

Page 181: ...r Circuit for Mode 0 In mode 0 RXD must be enabled for receptions and disabled for transmissions See Program ming the Control Register on page 7 8 When RXD is enabled either a rising edge on the RXD i...

Page 182: ...ort sets an interrupt pending bit only if the ninth data bit is set In mode 3 the serial port always sets an interrupt pending bit upon completion of a data transmission or reception When the serial p...

Page 183: ...h one wire for transmit and receive The receiving processor must wait for one bit time after the RI flag is set before starting to transmit Otherwise the transmission could corrupt the stop bit causin...

Page 184: ...t During a transmission the TI flag and the TI interrupt pending bit are set at the beginning of the stop bit The ninth bit can be used for parity or multiprocessor communications 7 3 2 5 Multiprocess...

Page 185: ...elects the communication mode and enables or disables the receiver parity checking and nine bit data transmissions Selecting a new mode resets the serial I O port and aborts any transmission or recept...

Page 186: ...takes on the even parity value 3 REN Receive Enable Setting this bit enables the receiver function of the RXD pin When this bit is set a high to low transition on the pin starts a reception in mode 1...

Page 187: ...BAUD_VALUE is 0001H for transmissions and 0002H for receptions 15 8 CLKSRC BV14 BV13 BV12 BV11 BV10 BV9 BV8 7 0 BV7 BV6 BV5 BV4 BV3 BV2 BV1 BV0 Bit Number Bit Mnemonic Function 15 CLKSRC Serial Port C...

Page 188: ...le 7 3 shows the SP_BAUD values for common baud rates when using a 20 MHz XTAL1 clock input Because of rounding the BAUD_VALUE formula is not exact and the resulting baud rate is slightly different th...

Page 189: ...Received Parity Error Received Bit 8 RPE is set if parity is disabled SP_CON 2 0 and the ninth data bit received is high RB8 is set if parity is enabled SP_CON 2 1 and a parity error occurred Reading...

Page 190: ...t does not clear the corresponding interrupt pending bits The RI and TI flags in the SP_STATUS and the corresponding interrupt pending bits can be set even if the RI and TI interrupts are masked The t...

Page 191: ...latile register unsigned char wsr volatile unsigned char sbuf_tx sbuf_rx SP_STATUS sp_con volatile unsigned char int_mask1 int_pend1 volatile unsigned int sp_baud pragma locate sbuf_tx 0xba sbuf_rx 0x...

Page 192: ...e while instruction checks the case when the end index is one less than the beginning index and at the end of the buffer when the beginning index may be equal to 0 and the end buffer index may be at t...

Page 193: ...end_rec_buff 0 initialize buffer pointers begin_rec_buff 0 end_trans_buff 0 begin_trans_buff 0 status_temp TI_BIT allow for initial transmission int_mask1 0x18 enable the serial port interrupt enable...

Page 194: ...8 Synchronous Serial I O SSIO Port...

Page 195: ......

Page 196: ...provides for simultaneous bidirectional communications between this device and another synchronous serial I O device The SSIO port consists of two identical transceiver channels A single dedicated ba...

Page 197: ...SC1 I O SSIO1 Clock Pin This pin transmits a clock signal when SSIO1 is configured as a master and receives a clock signal when it is configured as a slave SC1 carries a clock signal only during recep...

Page 198: ...P6 4 for the SSIO P6_PIN 1FD7H Port 6 Pin State Read P6_PIN to determine the current values of SD1 P6 7 SC1 P6 6 SD0 P6 5 and SC0 P6 4 P6_REG 1FD5H Port 6 Output Data This register holds data to be d...

Page 199: ...r to communicate with compatible protocols in half duplex mode This mode requires one data input output pin and one clock input pin SD0 SC0 Master Slave SD0 SC0 Single channel Half duplex Master Slave...

Page 200: ...ls can operate with handshaking enabled in full duplex mode One channel acts as slave and the other acts as master This mode requires four pins The two channels can operate with handshaking enabled in...

Page 201: ...prevents a data overflow at the slave In the oppo site configuration the slave pulls the clock line low until its buffer is loaded with data This pre vents a data underflow at the slave 8 4 1 SSIO Ha...

Page 202: ...ars the transmit buffer status TBS bit in SSIOx_CON and indicates that SSIOx_BUF is available for another packet to be re ceived or transmitted When handshaking is enabled the master leaves its clock...

Page 203: ...BUF to RAM 2 You set the master s SSIOx interrupt pending bit in the INT_PEND1 register 3 The PTS transfers a byte to SSIOx_BUF 4 The slave pulls the clock line low until it is ready to receive a byte...

Page 204: ...on page 8 2 lists the pins associated with the SSIO port and Table 8 2 lists the port configu ration registers See Chapter 6 for configuration details 8 5 2 Programming the Baud Rate and Enabling the...

Page 205: ...BV3 BV2 BV1 BV0 Bit Number Bit Mnemonic Function 7 BE Baud rate Generator Enable This bit enables and disables the baud rate generator For write operations 0 disable the baud rate generator and clear...

Page 206: ...clock input to SSIOx_BUF 1 master SCx is an output driven by the SSIO baud rate generator 6 T R Transmit Receive Select Configures the channel as either transmitter or receiver 0 receiver SDx is an in...

Page 207: ...0 no overflow or underflow has occurred 1 the core attempted to access SSIOx_BUF during the current transfer or the master attempted to clock data into or out of the slave s SSIOx_BUF before the buff...

Page 208: ...G CONSIDERATIONS For transmissions the time that you write to SSIOx_BUF determines the data setup time the length of time between data being placed on the data pin and the first clock edge on the cloc...

Page 209: ...UF 3 Set the STE bit in SSIOx_CON This enables transfers and drives the MSB onto the data pin 4 Disable interrupts 5 Set the MSB of SSIO_BAUD and write the desired BAUD_VAL to the remaining bits This...

Page 210: ...reg equ 0d5h byte window to 1fd5h ssio_baud equ 0b4h byte window to 1fb4h ssio0_con equ 0b1h byte window to 1fb1h ssio1_con equ 0b3h byte window to 1fb3h ssio0_buf equ 0b0h byte window to 1fb0h ssio1_...

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Page 212: ...9 Slave Port...

Page 213: ......

Page 214: ...bus which requires even more pins than a simple parallel connection does The DPRAM is also costly and error de tection can be difficult The SSIO offers a simple means for implementing a serial link Th...

Page 215: ...d data input register are input only registers that are written when SLPCS and SLPWR are both low 9 2 SLAVE PORT SIGNALS AND REGISTERS Table 9 1 lists the signals used for slave port operation The bus...

Page 216: ...LP_CON SLP_ADDR SLPALE P5 0 SLP1 P3 1 SLPRD P5 3 SLPWR P5 2 SLPCS P5 1 SLP_STAT P3_REG Data Out P3_PIN Data In SLP_CMD OE OE WE WE Q Internal Bus 8XC196 Device D A0267 03 SLP7 0 P3 7 0 0 1 SLP_STAT 1...

Page 217: ...input to the slave Data from the P3_REG or SLP_STAT register is valid after the falling edge of SLPRD P5 4 SLPINT O Slave Port Interrupt This active high slave port output signal can be used to interr...

Page 218: ...d memory mode the master must first write 0 to the SLP1 pin SLP_CMD 1FFAH Slave Port Command Register This register accepts commands from the master to the slave The commands are defined by the device...

Page 219: ...peration by forcing SLPRD or SLPWR low respectively Data is latched on the rising edge of either SLPRD or SLPWR When the slave completes a read or a write it notifies the master via the SLPINT signal...

Page 220: ...Interrupt Output Master Processor or System Bus Slave Port Connections for Multiplexed Bus Interface LE Latched Address Decoder SLP7 0 SLPALE SLPRD SLPWR SLPCS SLPINT 8XC196 Slave Processor Data Bus...

Page 221: ...address to the slave s command register SLP_CMD This mode can be used with either a multiplexed or a demultiplexed bus In this example the master and slave share a 256 byte block of memory from 0400 0...

Page 222: ...E flag before it loads SLP_CMD Therefore only one of the two flags is clear when the CBF interrupt service routine is entered If the IBE flag is clear the input buffer P3_PIN is full the slave moves t...

Page 223: ...e temporary storage register and one byte for the base address A read requires 91 state times 9 1 s at 20 MHz and a write requires 86 state times 8 6 s at 20 MHz These times do not include interrupt l...

Page 224: ...When the master requests a read operation the data present during the current bus cycle is either dummy data or the data from the previous read operation Although read operations are pipelined write o...

Page 225: ...P3_REG register When the slave writes the P3_REG register it forc es SLPINT high which notifies the master that another operation can be performed Remember that read operations are pipelined The follo...

Page 226: ...nly one master bus cycle Figure 9 5 shows relative timing relationships Con sult the datasheet for actual timing specifications Figure 9 5 Standard or Shared Memory Mode Timings Multiplexed Bus A0306...

Page 227: ...ar the MSB of P34_DRV STB TEMP P34_DRV 0 make Port 3 open drain Once you have configured the pins you must initialize the registers This example shows the ini tialization code The remaining sections o...

Page 228: ...LPL Slave Port Latch In standard slave mode only this bit determines the source of the internal control signal SLP_ADDR When SLP_ADDR is held high the master can write to the SLP_CMD register and read...

Page 229: ...D SLAVE The status bits in the SLP_STAT register can be used to synchronize the master with the slave Because synchronization of the status bits is not monitored by the status flags it is more difficu...

Page 230: ...eived a read 1 or a write 0 SMO can be read but not written In standard slave mode bit 7 SF4 is the high bit of the status field 6 3 SF3 0 Status Field The slave can write to these bits for general pu...

Page 231: ......

Page 232: ...10 Event Processor Array EPA...

Page 233: ......

Page 234: ...for an event a rising edge a falling edge or an edge in either direction When the event occurs the EPA records the value of the timer counter so that the event is tagged with a time This is called an...

Page 235: ...first column Table 10 2 briefly describes the registers for the EPA capture compare channels EPA compare only channels and timer counters Indirect Interrupt Processor Logic EPAx Interrupt A0308 03 TIM...

Page 236: ...of the compare only channel 1 P6 2 T1CLK I External clock source for timer 1 P6 3 T1DIR I External direction control for timer 1 Table 10 2 EPA Control and Status Registers Mnemonic Address Descripti...

Page 237: ...o the correct interrupt service routine for the active interrupt INT_MASK 0008H Interrupt Mask Five bits in this register enable and disable mask the individual EPA0 EPA1 EPA2 and EPA3 interrupts and...

Page 238: ...E x initialize or overwrite the pin value then configure the pin as a special function signal set Px_MODE x In this way initialization fault recovery exception handling etc can be done without changin...

Page 239: ...ter if it is clocked externally Figure 10 2 illustrates the timer counter structure Figure 10 2 EPA Timer Counters T2CLK FOSC 4 Timer 1 Overflow T2DIR T2CONTROL 6 Timer 1 T1CLK FOSC 4 Prescaler Module...

Page 240: ...ing can pro vide a slow clock for idle mode timeout control or for slow pulse width modulation PWM ap plications see Generating a Low speed PWM Output on page 10 14 10 3 2 Quadrature Clocking Mode Bot...

Page 241: ...Table State of X_internal TxCLK State of Y_internal TxDIR Count Direction 0 Increment 1 Increment 0 Increment 1 Increment 0 Decrement 1 Decrement 0 Decrement 1 Decrement Optical Reader TxDIR TxCLK D...

Page 242: ...the event time register clear set or toggle the EPA pin when the timer value matches the programmed value in the event time register generate an interrupt when a capture or compare event occurs genera...

Page 243: ...compare channels 8 and 9 This means that both capture compare channel 8 and compare only channel 0 can set clear or toggle the EPA8 COMP0 pin They can operate at the same time and neither has priorit...

Page 244: ...EPA interrupt pending bit is set Figure 10 6 EPA Simplified Input capture Structure If a third event occurs before the CPU reads the event time register the overwrite bit EPAx_CON 0 determines how th...

Page 245: ...ata and no EPA interrupt is generated an input signal with a frequency high enough to cause overruns is present on an enabled EPA pin and the overwrite bit is set EPAx_CON 0 1 old data is overwritten...

Page 246: ...ted The OVRx interrupt will then be acknowledged and its interrupt service routine will read the EPAx_TIME regis ter After the CPU reads the EPAx_TIME register the buffered data moves from the buffer...

Page 247: ...vice execution time increases To determine the maximum low speed PWM frequency in your system calculate your system s worst case interrupt latency and worst case interrupt service execution time and t...

Page 248: ...ting a Medium speed PWM Output You can generate a medium speed pulse width modulated output with a single EPA channel and the PTS set up in PWM toggle mode PWM Toggle Mode Example on page 5 33 describ...

Page 249: ...imer counter is not interrupted during this process so other EPA channels can also use it if they do not reset it To determine the maximum high speed PWM frequency in your system calculate your system...

Page 250: ...pins of port 1 and port 6 to serve as the spe cial function signals for the EPA and optionally for the timer counter clock source and direction control signals See Bidirectional Ports 1 2 5 and 6 on...

Page 251: ...ts These bits determine the timer clocking source and direction control source M2 M1 M0 Clock Source Direction Source 0 0 0 FOSC 4 UD bit T1CONTROL 6 X 0 1 T1CLK Pin UD bit T1CONTROL 6 0 1 0 FOSC 4 T1...

Page 252: ...er clocking source and direction source M2 M1 M0 Clock Source Direction Source 0 0 0 FOSC 4 UD bit T2CONTROL 6 X 0 1 T2CLK Pin UD bit T2CONTROL 6 0 1 0 FOSC 4 T2DIR Pin 0 1 1 T2CLK Pin T2DIR Pin 1 0 0...

Page 253: ...5 shows the effects of various combinations of EPAx_CON bit settings Table 10 5 Example Control Register Settings and EPA Operations Capture Mode TB CE MODE RE AD ROT ON RT Operation 7 6 5 4 3 2 1 0...

Page 254: ...feature of EPA1 is enabled EPA capture compare channel 0 shares output pin EPA1 with EPA capture compare channel 1 When the remap feature of EPA3 is enabled EPA capture compare channel 2 shares output...

Page 255: ...me the event time register EPAx_TIME matches the reference timer rather than only upon the first time match 0 compare function is disabled after a single event 1 compare function always enabled EPAx_C...

Page 256: ...pposite timer for possible reset The TB bit bit 7 selects which is the reference timer and which is the opposite timer EPAx_CON Continued x 0 9 Address Reset State See Table 10 2 on page 10 3 F700H x...

Page 257: ...T selected timer EPAx_CON Continued x 0 9 Address Reset State See Table 10 2 on page 10 3 F700H x 1 3 00H x 0 2 4 9 The EPA control EPAx_CON registers control the functions of their assigned capture c...

Page 258: ...is the opposite timer 1 timer 2 is the reference timer and timer 1 is the opposite timer A compare event start of an A D conversion clearing setting or toggling an output pin and or resetting either...

Page 259: ...EPA as the conversion source in the AD_CONTROL register 1 EPA compare event triggers an A D conversion 0 causes no A D action 1 ROT Reset Opposite Timer Selects the timer that is to be reset if the RT...

Page 260: ...VR2 OVR3 OVR4 OVR5 OVR6 OVR7 OVR8 OVR9 Bit Number Function 15 10 Setting this bit enables the corresponding interrupt as a multiplexed EPAx interrupt source The multiplexed EPAx interrupt is enabled b...

Page 261: ...A9 OVR0 OVR1 7 0 OVR2 OVR3 OVR4 OVR5 OVR6 OVR7 OVR8 OVR9 Bit Number Function 15 10 Any set bit indicates that the corresponding EPAx interrupt source is pending The bit is cleared when the EPA interru...

Page 262: ...e interrupt source Ta ble 10 6 For example assume that an overrun occurs on capture compare channel 9 and no other multi plexed interrupt is pending and unmasked This sets the OVR9 pending bit in the...

Page 263: ...bit is also cleared 7 0 PV4 PV3 PV2 PV1 PV0 Bit Number Bit Mnemonic Function 5 7 Reserved always write as zeros 4 0 PV4 0 Priority Vector These bits contain a number from 01H to 14H corresponding to...

Page 264: ...7 bit immediate data to mask the index This value is ANDed with the 7 bit value pointed to by index and the instruction multiplies the result by two to determine the offset into the jump table TIJMP...

Page 265: ...obally enabled and the capture compare channel 0 has generated an OVR0 interrupt This interrupt occurs when an edge is detected on the EPA channel and both the input buffer and EPA0_TIME are full This...

Page 266: ...m were written in the C programming lan guage ASM versions are also available from ApBUILDER NOTE The initialization file 80c196kr h used in these examples is available from the Intel Applications BBS...

Page 267: ...PA channel 0 to capture edges rising and falling on the EPA0 pin The program also shows how to set up the EPA inter rupts You can add your own code for the interrupt service routine pragma model inclu...

Page 268: ...the EPA s PWM toggle mode see PWM Modes on page 5 31 and shows how to service the interrupts with the PTS The PWM signal in this example has a 50 duty cycle pragma model EX include 80c196kr h define P...

Page 269: ...M_toggle_CB_3 pts_ptr void EPA0_TIME PWM_toggle_CB_3 ptscon 0x42 Sample code that could be used to generate a PWM with an EPA channel setbit p1_reg 0x1 init output clrbit p1_dir 0x1 set to output setb...

Page 270: ...11 Analog to digital Converter...

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Page 272: ...ogram it 11 1 A D CONVERTER FUNCTIONAL OVERVIEW The A D converter Figure 11 1 can convert an analog input voltage to an 8 or 10 bit digital result and set the A D interrupt pending bit when it stores...

Page 273: ...ects the operating mode AD_RESULT 1FAAH 1FABH A D Result For an A D conversion the high byte contains the eight MSBs from the conversion while the low byte contains the two LSBs from a 10 bit conversi...

Page 274: ...ed samples or synchronization with external events See Programming the EPA and Timer Counters on page 10 17 The A D scan mode of the pe ripheral transaction server PTS allows you to perform multiple c...

Page 275: ...ult where the most significant bit is zero and all other bits are ones 0111111111B If the analog input was less than the test voltage bit 10 of the SAR is left at zero and a new test voltage of full s...

Page 276: ...enables conversions on ANGND and VREF and specifies adjustments for DC offset errors Its functions allow you to perform two conversions one on ANGND and one on VREF With these results a software routi...

Page 277: ...for the comparator and cir cuitry to settle and resolve the voltage Excessively long conversion times allow the sample ca pacitor to discharge degrading accuracy AD_RESULT Write Address Reset State 1F...

Page 278: ...7 TSAM the sample time in sec from the data sheet FOSC the XTAL1 frequency in MHz 4 0 CONV4 0 A D Convert Time These bits specify the conversion time for each bit Use the following formula to compute...

Page 279: ...1 1 threshold detect low 3 GO A D Conversion Trigger Note 2 Writing this bit arms the A D converter The value that you write to it determines at what point a conversion is to start 1 start immediatel...

Page 280: ...interrupts and a description of using the PTS in A D scan mode 11 5 DETERMINING A D STATUS AND CONVERSION RESULTS You can read the AD_RESULT register Figure 11 6 to determine the status of the A D con...

Page 281: ...sists of two bytes The high byte contains the eight most significant bits from the A D converter The low byte contains the two least significant bits from a ten bit A D conversion indicates the A D ch...

Page 282: ...ealized A D Sampling Circuitry During the sample window the external input circuit must be able to charge the sample capacitor CS through the series combination of the input source resistance RSOURCE...

Page 283: ...mula If CEXT is 0 005 F or greater the error will be less than 0 4 LSB in 10 bit conversion mode The use of CEXT in conjunction with RSOURCE forms a low pass filter that reduces noise input to the A...

Page 284: ...to the internal reference circuitry and substantially degrades the accuracy of A D conversions on all channels Figure 11 8 Suggested A D Input Circuit 11 6 1 3 Analog Ground and Reference Voltages Ref...

Page 285: ...NGND not to VSS to ensure that VREF tracks ANGND and not VSS 11 6 1 4 Using Mixed Analog and Digital Inputs Port 0 may be used for both analog and digital input signals at the same time However readin...

Page 286: ...et er ror full scale error differential nonlinearity and nonlinearity All of these are transfer function errors related to the A D converter In addition temperature coefficients VCC rejection sample h...

Page 287: ...d its code widths are all exactly one LSB These qualities result in a digitization without zero offset full scale or linearity errors in other words a perfect conversion FINAL CODE TRANSITION OCCURS W...

Page 288: ...re 11 10 The deviation of the first code transition from ideal is called zero offset error and the deviation of the final code transition from ideal is full scale error The deviation of a code width f...

Page 289: ...y subsequent code change represents an input voltage change in the same direction Differential nonlinearity and nonlinearity are quantified by measuring the terminal based linear ity errors A terminal...

Page 290: ...2 0 1 2 3 4 5 6 7 INPUT VOLTAGE LSBs OUTPUT CODE Q IDEAL STRAIGHT LINE TRANSFER FUNCTION NON LINEARITY DIFFERENTIAL NON LINEARITY POSITIVE IDEAL CODE WIDTH IDEAL FIRST TRANSITION IDEAL CODE WIDTH DIFF...

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Page 292: ...12 Minimum Hardware Considerations...

Page 293: ......

Page 294: ...tate times In the powerdown and idle modes asserting RESET causes the chip to reset and return to normal operating mode The microcontroller resets to FF2080H in internal OTPROM or F2080H in external m...

Page 295: ...signal When using an external clock source instead of the on chip oscillator connect the clock input to XTAL1 The external clock signal must meet the VIH specification for XTAL1 see datasheet XTAL2 O...

Page 296: ...1 See the datasheet for the oscillator frequency range FOSC and the crystal manufacturer s datasheet for recommended load capacitors 2 The number of VCC and VSS pins varies with package type see data...

Page 297: ...e fast rise and fall times of high speed CMOS logic often produce noise spikes on the power supply lines and outputs To minimize noise it is important to follow good design and board lay out technique...

Page 298: ...P 711 EMI Design Techniques for Microcontrollers in Auto motive Applications 12 4 PROVIDING THE CLOCK The device can either use the on chip oscillator to generate the clocks or use an external clock i...

Page 299: ...ually adequate for frequencies above 1 MHz Noise spikes on the XTAL1 or XTAL2 pin can cause a miscount in the internal clock generating circuitry Capacitive coupling between the crystal oscillator and...

Page 300: ...m rise and fall transition times TXLHX and TXHXL Figure 12 6 The longer the rise and fall times the higher the probability that external noise will affect the clock generator circuitry and cause unrel...

Page 301: ...ted the I O pins the con trol pins and the registers are driven to their reset states Table B 6 on page B 14 lists the reset states of the pins See Table C 2 on page C 2 for the reset values of the SF...

Page 302: ...llator fail detect OFD circuitry is enabled and an oscillator failure occurs The following paragraphs describe each of these reset methods in more detail RESET Pin Case 1 CLKOUT Case 2 CLKOUT Internal...

Page 303: ...insert a capacitor between the RESET pin and VSS as shown in Figure 12 9 The device has an internal pull up resistor RRST shown in Figure 12 8 RESET should remain asserted for at least one state time...

Page 304: ...system reset circuit In this example D2 creates a wired OR gate connection to the reset pin An internal reset system power up or SW1 closing will generate the system reset signal Figure 12 10 Example...

Page 305: ...ly or is disabled until the first time it is cleared Clearing WDE activates the watchdog Setting WDE makes the watchdog timer inactive but you can activate it by clearing the watchdog register Once th...

Page 306: ...13 Special Operating Modes...

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Page 308: ...ime is one state time If the chip is in idle mode and if EXTINT is enabled a rising edge on EXTINT brings the chip back to normal operation where the first action is to execute the EXTINT service rout...

Page 309: ...s Use this method to exit powerdown only when using an external clock source because it enables the internal phase clocks but not the internal oscillator On devices with no internal nonvolatile memory...

Page 310: ...n Internal logic holds the CPU clocks at logic zero causing the CPU to stop executing instructions Neither the peripheral clocks nor CLKOUT are affected so the special function reg isters SFRs and reg...

Page 311: ...XTINT low while the device is in idle mode 13 4 POWERDOWN MODE Powerdown mode places the device into a very low power state by disabling the internal oscilla tor and clock generators Internal logic ho...

Page 312: ...es to control the bus while the microcontroller is in powerdown assert HLDA Do this only if the routines for entering and exiting powerdown do not require access to external memory After completing th...

Page 313: ...but the pin must be configured as a special function input see Bidirectional Port Pin Configura tions on page 6 9 Figure 13 2 shows the power up and powerdown sequence when using an external interrup...

Page 314: ...pin voltage drops below the threshold voltage about 2 5 V the internal phase clocks are enabled and the device resumes code execution At this time the internal pull up transistor turns on and quickly...

Page 315: ...a to calculate an appropriate value for C1 where C1 is the capacitor value in farads TDIS is the worst case discharge time in seconds I is the discharge current in amperes Vt is the threshold voltage...

Page 316: ...dental entry into ONCE mode we highly recommend configuring this pin as an output If you choose to configure this pin as an input always hold it high during reset and ensure that your system meets the...

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Page 318: ...14 Interfacing with External Memory...

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Page 320: ...er 20 address lines A19 16 and AD15 0 are implemented with external pins The absence of the upper four address bits at the external pins causes different internal addresses to have the same external a...

Page 321: ...3 0 EPORT 3 0 AD15 0 I O Address Data Lines These pins provide a multiplexed address and data bus During the address phase of the bus cycle address bits 0 15 are presented on the bus and can be latche...

Page 322: ...ice can assert BREQ at the same time as or after it asserts HLDA Once it is asserted BREQ remains asserted until HOLD is removed You must enable the bus hold protocol before using this signal see Enab...

Page 323: ...quires use of the external bus How quickly the 8XC196NT asserts INTOUT depends upon the status of HOLD and HLDA and whether the device is executing from internal or external program memory If the 8XC1...

Page 324: ...peration continues in a normal manner with wait states inserted as programmed in the chip configuration registers READY is ignored for all internal memory accesses P5 6 WR O Write The chip configurati...

Page 325: ...along with IRC2 CCR1 1 limit the number of wait states that can be inserted while the READY pin is held low Wait states are inserted into the bus cycle either until the READY pin is pulled high or un...

Page 326: ...ode Clearing this bit at reset can prevent accidental entry into powerdown mode 1 enable powerdown mode 0 disable powerdown mode CCR0 Continued Address Reset State FF2018H XXH The chip configuration 0...

Page 327: ...s timing modes MSEL1 MSEL0 0 0 standard mode plus one wait state 0 1 long read write 1 0 long read write with early address 1 1 standard mode 5 0 To guarantee device operation write zero to this bit 4...

Page 328: ...llegal 1 1 X illegal 1 0 0 one wait state 1 0 1 two wait states 1 1 0 three wait states 1 1 1 infinite 0 LDCCB2 Load CCB2 Setting this bit causes CCB2 to be read CCR1 Continued Address Reset State FF2...

Page 329: ...internal OTPROM is mapped into both page 0FFH and page 00H or into page FFH only This register is loaded from CCB2 if the LDCCB2 bit bit 0 of CCR1 is set otherwise it is loaded with FFH 7 0 REMAP MOD...

Page 330: ...gures 14 1 and 14 2 If BW0 is clear and BW1 is set the bus controller is locked into an 8 bit bus mode In comparing an 8 bit bus system to a 16 bit bus system expect some performance degradation In a...

Page 331: ...ust be met for proper operation see Figure 14 5 Because a decoded valid ad dress is used to generate the BUSWIDTH signal the setup time is specified relative to the address being valid This specificat...

Page 332: ...nal is used to strobe a transparent latch such as a 74AC373 which captures the address from AD15 0 and holds it while the bus controller puts data onto AD15 0 For 16 bit read cycles the bus controller...

Page 333: ...4 Figure 14 6 Timings for 16 bit Buses XTAL1 CLKOUT ALE BUSWIDTH Bus AD15 0 Read RD INST Bus AD15 0 Write WR Address Out Data Out Data In Address Out Valid A19 16 Extended Address Out A19 16 Extended...

Page 334: ...as on the 16 bit bus The ALE signal is used to demultiplex the lower address by strobing a transparent latch such as a 74AC373 For 8 bit bus read cycles after ALE falls the bus controller floats the...

Page 335: ...AD15 8 RD INST Bus AD7 0 Write WR Address Out Address Out Low data in Address Out Low data out Bus AD7 0 Read XTAL1 Address 1 Out High data out High data in Address Out Address 1 Out A19 16 Extended A...

Page 336: ...finite number of wait states to be inserted into bus cycles and the chip to lock up After the CCB1 fetch the internal ready control circuitry allows slow external memory devices to increase the length...

Page 337: ...TCLYX timing specification is met Typically this is a minimum of 0 ns from the time CLKOUT goes low Do not exceed the maxi mum TCLYX specification or additional unwanted wait states might be added In...

Page 338: ...device bus it asserts the HOLD signal HOLD is sampled while CLKOUT is low The device responds by releasing the bus and asserting HLDA During this hold time the address data bus floats and signals ALE...

Page 339: ...CLKOUT Low to HLDA High TCLBRL CLKOUT Low to BREQ Low TCLBRH CLKOUT Low to BREQ High THALAZ HLDA Low to Address Float CLKOUT HOLD HLDA BREQ Bus BHE INST RD WR WRL WRH ALE TCLLH TCLHAH TCLBRH THAHAX T...

Page 340: ...LDA and INTOUT and waits until the external device deasserts HOLD to deassert HLDA and INTOUT 14 6 1 Enabling the Bus hold Protocol To use the bus hold protocol you must configure P2 3 BREQ P2 5 HOLD...

Page 341: ...ency When an external device asserts HOLD the device finishes the current bus cycle and then as serts HLDA The time it takes the device to assert HLDA after the external device asserts HOLD is called...

Page 342: ...e generated during external read and write cycles Table 14 6 lists the four bus control modes and shows the CCR0 3 and CCR0 2 settings for each 14 7 1 Standard Bus control Mode In the standard bus con...

Page 343: ...oduce these signals WRL and WRH A similar pair of signals for read is unneces sary For a single byte read with the 16 bit bus both bytes are placed on the data bus and the pro cessor discards the unwa...

Page 344: ...cause these lines are carry both address and data information The upper address lines AD15 8 are latched only when operating in bus timing modes 1 and 2 because in these modes the address lines are no...

Page 345: ...w memory It is selected by driving A19 low which also selects the 8 bit bus width mode by driving the BUSWIDTH signal low Figure 14 13 16 bit System with Dynamic Bus Width A0286 02 AD15 8 RD ALE 74AC...

Page 346: ...WRL is asserted for all low byte writes even addresses and all word writes WRH is asserted for all high byte writes odd addresses and all word writes In the 8 bit bus mode WRH and WRL are asserted fo...

Page 347: ...writes and word writes Note that the RAM devices do not use AD0 WRL and WRH de termine whether the low byte AD0 0 or high byte AD0 1 is selected Figure 14 15 16 bit System with Single byte Writes to...

Page 348: ...fference between ALE and ADV is that ADV is asserted for the entire bus cycle not just to latch the address Figure 14 17 shows the difference between ALE and ADV for a single read or write cycle Note...

Page 349: ...8XC196NT USER S MANUAL 14 30 Figure 14 17 Comparison of ALE and ADV Bus Cycles Address Data ADV ALE RD WR Extended Address Next Bus Cycle Bus Idle A0290 02 AD15 0 A19 16...

Page 350: ...h signal The lower address lines AD7 0 are latched because these lines are carry both address and data information The upper address lines AD15 8 are latched only when op erating in bus timing modes 1...

Page 351: ...DV signal as both the flash chip select signal and the address latch signal Figure 14 19 16 bit System with Flash A0292 02 VCC AD7 0 AD15 8 RD ADV 74AC 373 74AC 373 A14 7 A14 7 D15 8 D7 0 A6 0 A6 0 CS...

Page 352: ...tem using external 16 bit RAM Figure 14 20 shows the timing The RD signal not shown is similar to WRL WRH and WR The example system of Figure 14 21 uses address valid with write strobe Figure 14 20 Ti...

Page 353: ...Figure 14 2 on page 14 8 defines these bit settings The remainder of this section describes each mode Figure 14 22 illustrates the modes together and Table 14 7 summarizes the differences in their tim...

Page 354: ...ODE 3 MODE 0 MODE 1 MODE 2 TRLDV 1 TOSC TAVDV 3 TOSC TRLDV 2 TOSC TRLDV 3 TOSC TAVDV 3 TOSC TAVDV 3 5 TOSC TRHDZ 1 2 TOSC 1 2 TOSC TAVDV 5 TOSC TRHDZ 1 TOSC TRHDZ 1 TOSC DATA DATA DATA ADDR ADDR DATA...

Page 355: ...ode RD WR and ALE begin TOSC earlier in the bus cycle and the width of RD and WR are 1 TOSC longer than in mode 3 The TRLDV timing is 1 TOSC longer in mode 1 than in mode 3 allowing the memory more ti...

Page 356: ...in the bus cycle The TRLDV timing is 1 TOSC longer the TAVDV timing is TOSC longer and TRHDZ is TOSC shorter in mode 2 than in mode 3 This mode trades a longer TAVDV for a shorter TRHDZ XTAL 1 CLKOUT...

Page 357: ...HDZ TLLAX TAVLL TAVDV TLLWL TWLWH Address Out Data Out TQVWH TWHQX TOSC TCLLL Data In D15 0 TCHLH Address TXHCH TCHCL Bus Write AD15 0 8 and 16 bit Bus Mode TWHBX TRHBX TWHAX TRHAX TWHIX TRHIX AD15 0...

Page 358: ...y to latch the upper address lines because these lines are driven throughout the entire bus cycle 14 9 SYSTEM BUS AC TIMING SPECIFICATIONS Refer to the latest data sheet for the AC timings to make sur...

Page 359: ...Definition The External Memory System Must Meet These Specifications TAVDV Address Valid to Input Data Valid Maximum time the memory device has to output valid data after the 8XC196NT outputs a valid...

Page 360: ...w to WR Low Length of time after ALE ADV falls before WR is asserted Could be needed to ensure that proper memory decoding takes place before a device is enabled TQVWH Data Valid to WR High Time betwe...

Page 361: ...going inactive and next ALE ADV Also used to calculate WR inactive and next address valid TWHQX Data Hold after WR High Length of time after WR rises that the data stays valid on the bus TWLWH WR Low...

Page 362: ...15 Programming the Nonvolatile Memory...

Page 363: ......

Page 364: ...m page 15 9 programming mode pins page 15 11 entering programming modes page 15 13 slave programming page 15 15 auto programming page 15 25 serial port programming page 15 31 run time programming page...

Page 365: ...and read the data via the RXD P2 1 pin Customers typically use this mode to download large sections of code to the microcontroller during software development and testing You can also program individ...

Page 366: ...CBs using any of the programming methods but only slave programming mode allows you to program the PCCBs NOTE The developers have made a substantial effort to provide an adequate program protection sc...

Page 367: ...m counter the bus controller might prevent code execution from the last four bytes of internal memory The interrupt vectors and CCBs are not read protected because interrupts can occur even when execu...

Page 368: ...ternally supplied security key regardless of the CCB0 lock bits If the security keys match the routine continues otherwise the device enters an endless internal loop If you want to allow slave and aut...

Page 369: ...3 2 Controlling Fetches from External Memory Two UPROM bits disable external instruction fetches and external data fetches If you program the UPROM bits an attempt to fetch data or instructions from...

Page 370: ...contains two bits that disable external fetches of data and instructions and another that detects a failed oscillator These bits can be programmed but cannot be erased WARNING These bits can be progr...

Page 371: ...ays be set the remaining bits constitute the PPW_VALUE To determine the correct PPW_VALUE for the fre quency of the device use the following formula and round the result to the next higher integer whe...

Page 372: ...PPW register is loaded from the internal test ROM in serial port programming mode The default pulse width for serial port programming is longer than required so you should change the value before begi...

Page 373: ...pulse until PROG is deasserted In slave programming mode the PALE signal controls the pulse width In all cases the pulse width must be at least 100 s for successful programming A0190 03 Return From A...

Page 374: ...Description P0 7 4 PMODE 3 PMODE 0 I All Programming Mode Select Determines the programming mode PMODE is sampled after a device reset and must be static while the part is operating Table 15 6 on pag...

Page 375: ...ing of sequential OTPROM locations without requiring address transactions across the PBUS for each read or write AINC is sampled after each location is programmed or dumped If AINC is asserted the add...

Page 376: ...7 0 PBUS I O Auto ROM dump Address Command Data Bus During auto programming and ROM dump ports 3 and 4 serve as a regular system bus to access external memory P4 6 and P4 7 are left unconnected P1 2...

Page 377: ...tor must be stable before RESET rises The power supplies to the VCC VPP EA and RESET pins must be well regulated and free of glitches and spikes All VSS pins must be well grounded 15 7 2 1 Power up Se...

Page 378: ...security key might accidentally be written rendering the device inaccessible for further programming To prevent this possibility during slave programming program the rest of the OTPROM array before y...

Page 379: ...frequencies Figure 15 5 Slave Programming Circuit Table 15 7 Device Signature Word and Programming Voltages Device Signature Word Programming VCC Programming VPP Location Value Location Value Location...

Page 380: ...the CCRs from the CCBs for normal operation and from the PCCBs when entering programming modes You can program the CCBs using any of the pro gramming methods but only slave mode allows you to program...

Page 381: ...mode PCCB default is 16 bit addressing MSEL1 0 External Access Timing Mode Select PCCB default is standard mode WDE Watchdog Timer Enable PCCB default is initially disabled enabled the first time WDT...

Page 382: ...m word routine Figure 15 8 checks the CCB security lock bits If either security lock bit CCB0 6 or CCB0 7 has been programmed you must provide a matching security key to gain access to the device Usin...

Page 383: ...Address Command Decoding Routine Yes No Other Modes A0193 02 PMODE 05H PALE P2 1 0 Yes PVER P2 0 1 Yes Read Data From PBUS No PALE P2 1 0 Check Address P3 0 1 Yes Program Word Routine No Dump Word Rou...

Page 384: ...Enabled Yes Verify Security Key Keys Match Yes Programming Verifies Yes No Loop Forever No Deassert PVER P2 0 0 PROG P2 2 0 Yes No Yes Yes To Address Command Decoder PALE P2 1 0 AINC P2 4 0 Increment...

Page 385: ...ne verifies the contents of the location that was just programmed and asserts PVER to indicate successful programming AINC is optional and can automatically increment the address for the next location...

Page 386: ...rd Routine A0189 03 Yes Lock Bits Enabled No PROG P2 2 0 Yes Get Data from OPTROM Yes PROG P2 2 1 PALE P2 1 0 Yes No No Increment Address by 2 AINC P2 4 0 No Yes To Address Command Decoder From Addres...

Page 387: ...he timing mnemonics used in the program word and dump word waveforms The datasheets include timing specifications for these signals Table 15 9 Timing Mnemonics Mnemonic Description TSHLL Reset High to...

Page 388: ...specifications Tie the BUSWIDTH pin low to configure an 8 bit data bus Connect P1 1 and P1 2 as shown to generate the high order bits of the external EPROM address Connect P0 7 4 to VSS and VCC to sel...

Page 389: ...0 PVER RESET 12 50V 100 k 1 k 10 F 74HC14 1 0 F Reset EA VPP VREF P0 7 PMODE 3 P0 6 PMODE 2 P0 5 PMODE 1 P0 4 PMODE 0 ANGND READY P5 6 NMI BUSWIDTH P5 7 RD P5 3 P1 2 P1 1 AD13 8 87C196 Device A7 0 ALE...

Page 390: ...he verification fails the device enters an endless internal loop If the security keys match the routine continues The auto programming routine uses the modified quick pulse algorithm and the pulse wid...

Page 391: ...1 03 PMODE 0CH No Lock Bits Enabled Load PPW Yes No Pass Yes Verify Security Key Assert PACT Get External Data No Yes Data 0FFFFH Execute Modified Quick Pulse Algorithm then Return Yes Top of OTPROM N...

Page 392: ...an unknown security key might accidentally be written rendering the device inaccessible for further programming To minimize this possibility follow this recommended programming procedure NOTE All addr...

Page 393: ...ctions of the PMODE P0 7 4 pins To select ROM dump mode PMODE 6H connect P0 6 and P0 5 to VCC and connect P0 7 and P0 4 to ground The same bank switching mechanism is used and the memory map is the sa...

Page 394: ...PROM to customize code for a particular module Programming more than 2 Kbytes of OTPROM is not recommended in this mode because of its relatively long programming time Entering serial port programming...

Page 395: ...7 2 6 1 1 8k 1 8k 1 8k 1 8k 1 8k 10 F A0298 04 RXD TXD RXD TXD VCC 87C196 Device 30 pF 30 pF XTAL1 XTAL2 P0 7 PMODE 3 P0 6 PMODE 2 P0 5 PMODE 1 P0 4 PMODE 0 ANGND VREF VCC A B C VCC VPP EA 0 01 F VPP...

Page 396: ...ault programming pulse width is longer than required To avoid unnecessarily long pro gramming times change the default value before beginning to program the device For a 100 s pulse width use the foll...

Page 397: ...registers for serial port programming mode Pro grams executing from internal RAM should not alter these locations 15 10 4 Reduced Instruction Set Monitor RISM When you enter serial port programming m...

Page 398: ...Now you must transfer the address from the DATA register to the ADDR register 5CH by sending the DATA_TO_ADDR command 0AH 15 10 5 RISM Command Descriptions Table 15 14 lists and describes the RISM co...

Page 399: ...ation VPP must be at 12 5 volts To write to an internal RAM location VPP can be at either 5 0 volts or 12 5 volts 08H WRITE_WORD Puts the low word of the DATA register into the memory address pointed...

Page 400: ...DR register into the ADDR register Memory Addr ADDR 2217 2216 Before command 22 16 80 09 After command 80 09 80 09 12H GO PUSHes the user PC PSW and WSR onto the stack and starts your program from the...

Page 401: ...is actually 2080H of the program in OTPROM This example assumes that the word at location 2080H is 8067H the assembled hex value of the code No OTPROM locations are changed so VPP can be either 12 5 v...

Page 402: ...to itself to keep program running indefinitely The hex file must be loaded one byte at a time using the RISM commands Send Comments Example 2 DATA ADDR A0 Data High byte of address to DATA register A0...

Page 403: ...n 0400H 04 00 A1 22 04 00 08 WRITE_WORD Low word of DATA to memory location 0400 contents of ADDR Increment ADDR by two 04 00 A1 22 04 00 Memory Addresses 0401 0400 A1 22 04 02 00 SET_DLE_FLAG Next da...

Page 404: ...for location 0405H 22 11 80 27 04 04 FE Data Low byte of hex file for location 0404H 11 80 27 FE 04 04 08 WRITE_WORD Low word of DATA to memory location 0404 contents of ADDR Increment ADDR by two 11...

Page 405: ...ram in examples 3 and 4 attempted to write OTPROM location A500H with the value 1122H Changing the contents of location A500H alters any code programmed at 2500H because that location has been remappe...

Page 406: ...e approximately 100 s in duration Figure 15 15 is a run time programming example It performs five programming cycles for each word After each programming cycle the code causes the device to enter idle...

Page 407: ...ming cycles ANDB INT_PEND CLEAR_EPA0 clear EPA0 pending bit LDB INT_MASK ENABLE_EPA0 enable EPA0 interrupt LDB EPA0_CON EPA0_TIMER set up EPA0 as software timer LOOP LD TEMP0 TIMER1 load TIMER1 value...

Page 408: ...A Instruction Set Reference...

Page 409: ......

Page 410: ...jump instructions Table A 4 on page A 5 defines the symbols used in Table A 6 Table A 5 on page A 6 defines the variables used in Table A 6 to represent instruction operands Table A 6 beginning on pag...

Page 411: ...in ix 9x ORB XORB di im in ix di im in ix Ax LD ADDC di im in ix di im in ix Bx LDB ADDCB di im in ix di im in ix Cx ST BMOV ST STB CMPL STB di in ix di in ix Dx JNST JNH JGT JNC JNVT JNV JGE JNE Ex D...

Page 412: ...2op Note 2 di im in ix di im in ix 8x CMP DIVU Note 2 di im in ix di im in ix 9x CMPB DIVUB Note 2 di im in ix di im in ix Ax SUBC LDBZE di im in ix di im in ix Bx SUBCB LDBSE di im in ix di im in ix...

Page 413: ...icant bit of the operand changes during the shift For divide operations the quotient is stored in the low order half of the destination operand and the remainder is stored in the high order half The o...

Page 414: ...r bit 1 specified register bit 0 JNC C 0 C 1 JNH C 0 OR Z 1 C 1 AND Z 0 JC C 1 C 0 JH C 1 AND Z 0 C 0 OR Z 1 JGE N 0 N 1 JGT N 0 AND Z 0 N 1 OR Z 1 JLT N 1 N 0 JLE N 1 OR Z 1 N 0 AND Z 0 JNST ST 0 ST...

Page 415: ...alue must be in the range of 00 FCH ptr2_reg A double pointer register used with the EBMOVI instruction Must be aligned on an address that is evenly divisible by 8 The value must be in the range of 00...

Page 416: ...lag Settings Z N C V VT ST ADDB 2 operands ADD BYTES Adds the source and destination byte operands and stores the sum into the destination operand DEST DEST SRC DEST SRC ADDB breg baop 011101aa baop b...

Page 417: ...gs Z N C V VT ST 0 0 AND 3 operands LOGICAL AND WORDS ANDs the two source word operands and stores the result into the destination operand The result has ones in only the bit positions in which both o...

Page 418: ...sfers The blocks of data can be located anywhere in page 00H of register RAM but should not overlap Because the source SRCPTR and destination DSTPTR pointers are 16 bits wide this instruction uses non...

Page 419: ...ies use the EBMOVI instruction PTSSRC and PTSDST will operate from the page defined by EP_REG EP_REG should be set to 00H to select page 00H see Accessing Data on page 4 24 COUNT CNTREG LOOP SRCPTR PT...

Page 420: ...LRC 11111000 PSW Flag Settings Z N C V VT ST 0 CLRVT CLEAR OVERFLOW TRAP FLAG Clears the overflow trap flag VT 0 CLRVT 11111100 PSW Flag Settings Z N C V VT ST 0 CMP COMPARE WORDS Subtracts the source...

Page 421: ...nds are specified using the direct addressing mode The flags are altered but the operands remain unaffected If a borrow occurs the carry flag is cleared otherwise it is set DEST SRC DEST SRC CMPL Dlre...

Page 422: ...performed concurrently low word DEST DEST SRC high word DEST DEST MOD SRC DEST SRC DIV lreg waop 11111110 100011aa waop lreg PSW Flag Settings Z N C V VT ST DIVB DIVIDE SHORT INTEGERS Divides the con...

Page 423: ...to the low order byte i e the byte with the lower address of the destination operand and the remainder into the high order byte The following two statements are performed concurrently low byte DEST DE...

Page 424: ...on and the target label effecting the jump The offset must be in the range of 128 to 127 COUNT COUNT 1 if COUNT 0 then PC PC 8 bit disp end_if DJNZW wreg cadd 11100001 wreg disp NOTE The displacement...

Page 425: ...TRS CNTREG EBMOVI prt2_reg wreg 11100100 wreg p2_reg NOTES The pointers are autoincre mented during this instruction However CNTREG is decre mented only when the instruc tion is interrupted When EBMOV...

Page 426: ...UPTS Enables interrupts following the execution of the next statement Interrupt calls cannot occur immediately following this instruction Interrupt Enable PSW 1 1 EI 11111011 PSW Flag Settings Z N C V...

Page 427: ...DB EXTENDED LOAD BYTE Loads the value of the source byte operand into the destination operand This instruction allows you to move data from anywhere in the 16 Mbyte address space into the lower regist...

Page 428: ...e leftmost byte operand into the destination rightmost operand This instruction allows you to move data from the lower register file to anywhere in the 16 Mbyte address space ext indirect DEST SRC ext...

Page 429: ...nter idle mode KEY 1 to enter powerdown mode KEY 2 to execute a reset sequence KEY any value other than 1 or 2 The bus controller completes any prefetch cycle in progress before the CPU stops or reset...

Page 430: ...hen PC PC 8 bit disp JBC breg bitno cadd 00110bbb breg disp NOTE The displacement disp is sign extended to 24 bits PSW Flag Settings Z N C V VT ST JBS JUMP IF BIT IS SET Tests the specified bit If the...

Page 431: ...he program counter the offset between the end of this instruction and the target label effecting the jump The offset must be in the range of 128 to 127 if Z 1 then PC PC 8 bit disp JE cadd 11011111 di...

Page 432: ...set and the zero flag is clear this instruction adds to the program counter the offset between the end of this instruction and the target label effecting the jump The offset must be in range of 128 t...

Page 433: ...this instruction adds to the program counter the offset between the end of this instruction and the target label effecting the jump The offset must be in the range of 128 to 127 if C 0 then PC PC 8 b...

Page 434: ...l instruction If the sticky bit flag is clear this instruction adds to the program counter the offset between the end of this instruction and the target label effecting the jump The offset must be in...

Page 435: ...n If the sticky bit flag is set this instruction adds to the program counter the offset between the end of this instruction and the target label effecting the jump The offset must be in range of 128 t...

Page 436: ...ogram counter the return address onto the stack then adds to the program counter the offset between the end of this instruction and the target label effecting the call The offset must be in the range...

Page 437: ...e value of the source byte operand and loads it into the destination word operand low byte DEST SRC high byte DEST 0 DEST SRC LDBZE wreg baop 101011aa baop wreg PSW Flag Settings Z N C V VT ST LJMP LO...

Page 438: ...waop 11111110 010011aa waop wreg lreg PSW Flag Settings Z N C V VT ST MULB 2 operands MULTIPLY SHORT INTEGERS Multiplies the source and destination short integer operands using signed arithmetic and s...

Page 439: ...DEST SRC1 SRC2 MULU lreg wreg waop 010011aa waop wreg lreg PSW Flag Settings Z N C V VT ST MULUB 2 operands MULTIPLY BYTES UNSIGNED Multiplies the source and destination operands using unsigned arith...

Page 440: ...ORMALIZE LONG INTEGER Normalizes the source leftmost long integer operand That is it shifts the operand to the left until its most significant bit is 1 or until it has performed 31 shifts If the most...

Page 441: ...nd and replaces the original destination operand with the result The result has a 1 in each bit position in which either the source or destination operand had a 1 DEST DEST OR SRC DEST SRC OR wreg wao...

Page 442: ...register pair This instruction increments the SP by 4 Interrupt calls cannot occur immediately following this instruction INT_MASK1 WSR SP SP SP 2 PSW INT_MASK SP SP SP 2 POPA 11110101 PSW Flag Setti...

Page 443: ...T_MASK1 WSR INT_MASK1 0 PUSHA 11110100 PSW Flag Settings Z N C V VT ST 0 0 0 0 0 0 PUSHF PUSH FLAGS Pushes the PSW onto the top of the stack then clears it Clearing the PSW disables interrupt servicin...

Page 444: ...stack then adds to the program counter the offset between the end of this instruction and the target label effecting the call The offset must be in the range of 1024 to 1023 64 Kbyte mode SP SP 2 SP...

Page 445: ...nt wreg or SHL wreg breg 00001001 breg wreg PSW Flag Settings Z N C V VT ST SHLB SHIFT BYTE LEFT Shifts the destination byte operand to the left as many times as specified by the count operand The cou...

Page 446: ...erand to the right as many times as specified by the count operand The count may be specified either as an immediate value in the range of 0 to 15 0FH inclusive or as the content of any register 10H 0...

Page 447: ...ration DEST 2 rep resents signed division PSW Flag Settings Z N C V VT ST 0 SHRAB ARITHMETIC RIGHT SHIFT BYTE Shifts the destination byte operand to the right as many times as specified by the count o...

Page 448: ...In this operation DEST 2 rep resents signed division PSW Flag Settings Z N C V VT ST 0 SHRB LOGICAL RIGHT SHIFT BYTE Shifts the destination byte operand to the right as many times as specified by the...

Page 449: ...and another shift cycle occurs the instruc tion sets the sticky bit flag In this operation DEST 2 rep resents unsigned division PSW Flag Settings Z N C V VT ST 0 0 SJMP SHORT JUMP Adds to the program...

Page 450: ...ACT WORDS Subtracts the source word operand from the destination word operand stores the result in the destination operand and sets the carry flag as the complement of borrow DEST DEST SRC DEST SRC SU...

Page 451: ...C V VT ST SUBC SUBTRACT WORDS WITH BORROW Subtracts the source word operand from the destination word operand If the carry flag was clear SUBC subtracts 1 from the result It stores the result in the...

Page 452: ...word register INDEX contains the 16 bit address that points to a register containing a 7 bit value This value is used to calculate the offset into the jump table Like TBASE INDEX can be located in RA...

Page 453: ...on is intended for use by development tools These tools may not support user application of this instruction PSW Flag Settings Z N C V VT ST XCH EXCHANGE WORD Exchanges the value of the source word op...

Page 454: ...and zeros in all other bit positions DEST DEST XOR SRC DEST SRC XOR wreg waop 100001aa waop wreg PSW Flag Settings Z N C V VT ST 0 0 XORB LOGICAL EXCLUSIVE OR BYTES XORs the source byte operand with...

Page 455: ...0A SHRA 0B XCH Indexed 0C SHRL 0D SHLL 0E SHRAL 0F NORML 10 Reserved 11 CLRB 12 NOTB 13 NEGB 14 XCHB Direct 15 DECB 16 EXTB 17 INCB 18 SHRB 19 SHLB 1A SHRAB 1B XCHB Indexed 1C EST Indirect 1D EST Inde...

Page 456: ...55 ADDB Immediate 3 ops 56 ADDB Indirect 3 ops 57 ADDB Indexed 3 ops 58 SUBB Direct 3 ops 59 SUBB Immediate 3 ops 5A SUBB Indirect 3 ops 5B SUBB Indexed 3 ops 5C MULUB Direct 3 ops 5D MULUB Immediate...

Page 457: ...ct 2 ops 7B SUBB Indexed 2 ops 7C MULUB Direct 2 ops 7D MULUB Immediate 2 ops 7E MULUB Indirect 2 ops 7F MULUB Indexed 2 ops 80 OR Direct 81 OR Immediate 82 OR Indirect 83 OR Indexed 84 XOR Direct 85...

Page 458: ...7 ADDC Indexed A8 SUBC Direct A9 SUBC Immediate AA SUBC Indirect AB SUBC Indexed AC LDBZE Direct AD LDBZE Immediate AE LDBZE Indirect AF LDBZE Indexed B0 LDB Direct B1 LDB Immediate B2 LDB Indirect B3...

Page 459: ...direct CB PUSH Indexed CC POP Direct CD BMOVI CE POP Indirect CF POP Indexed D0 JNST D1 JNH D2 JGT D3 JNC D4 JNVT D5 JNV D4 JNVT D5 JNV D6 JGE D7 JNE D8 JST D9 JH DA JLE DB JC DC JVT DD JV DE JLT DF J...

Page 460: ...OPA F6 IDLPD F7 TRAP F8 CLRC F9 SETC FA DI FB EI FC CLRVT FD NOP FE DIV DIVB MUL MULB Note 2 FF RST NOTES 1 This opcode is reserved but it does not generate an unimplemented opcode interrupt 2 Signed...

Page 461: ...ops 4 58 4 59 4 5A 5 6 5B SUBC 3 A8 4 A9 3 AA 4 5 AB SUBCB 3 B8 3 B9 3 BA 4 5 BB NOTES 1 Indirect normal and indirect autoincrement share the same opcodes as do short and long indexed modes Because wo...

Page 462: ...71 3 72 4 5 73 ANDB 3 ops 4 50 4 51 4 52 5 6 53 NEG 2 03 NEGB 2 13 NOT 2 02 NOTB 2 12 OR 3 80 4 81 3 82 4 5 83 ORB 3 90 3 91 3 92 4 5 93 XOR 3 84 4 85 3 86 4 5 87 XORB 3 94 3 95 3 96 4 5 97 Table A 8...

Page 463: ...s always have even addresses the address can be expressed in the upper seven bits the least significant bit determines the addressing mode Indirect normal and short indexed modes make the second byte...

Page 464: ...l Opcodes Continued NOTES 1 Indirect normal and indirect autoincrement share the same opcodes as do short and long indexed modes Because word registers always have even addresses the address can be ex...

Page 465: ...1 F7 Table A 8 Instruction Lengths and Hexadecimal Opcodes Continued NOTES 1 Indirect normal and indirect autoincrement share the same opcodes as do short and long indexed modes Because word register...

Page 466: ...o short and long indexed modes Because word registers always have even addresses the address can be expressed in the upper seven bits the least significant bit determines the addressing mode Indirect...

Page 467: ...imal Opcodes Continued NOTES 1 Indirect normal and indirect autoincrement share the same opcodes as do short and long indexed modes Because word registers always have even addresses the address can be...

Page 468: ...10 8 11 ADDC 4 5 6 8 7 9 6 8 7 9 ADDCB 4 4 6 8 7 9 6 8 7 9 CLR 3 CLRB 3 CMP 4 5 6 8 7 9 6 8 7 9 CMPB 4 4 6 8 7 9 6 8 7 9 CMPL 7 DEC 3 DECB 3 EXT 4 EXTB 4 INC 3 INCB 3 SUB 2 ops 4 5 6 8 7 9 6 8 7 9 SU...

Page 469: ...16 14 17 MULUB 3 ops 10 10 12 15 13 15 12 16 14 17 Logical Mnemonic Direct Immed Indirect Indexed Normal Autoinc Short Long Reg Mem Reg Mem Reg Mem Reg Mem AND 2 ops 4 5 6 8 7 9 6 8 7 9 AND 3 ops 5 6...

Page 470: ...toinc Short Long Reg Mem Reg Mem Reg Mem Reg Mem POP 11 13 15 14 16 14 16 15 17 POPA 18 POPF 10 PUSH 8 9 11 14 12 15 12 15 13 16 PUSHA 18 PUSHF 8 Table A 9 Instruction Execution Times in State Times C...

Page 471: ...exed Normal Autoinc ELD 6 9 8 11 8 11 ELDB 6 9 8 11 8 11 EST 6 9 8 11 8 11 ESTB 6 9 8 11 8 11 Mnemonic Direct Immed Indirect Indexed Normal Autoinc Short Long Reg Mem Reg Mem Reg Mem Reg Mem LD 4 5 5...

Page 472: ...16 Mnemonic Direct Immed Indirect Indexed Normal Autoinc Short Long LCALL 1 Mbyte mode 64 Kbyte mode 15 11 RET 1 Mbyte mode 64 Kbyte mode 16 11 SCALL 1 Mbyte mode 64 Kbyte mode 15 11 TRAP 1 Mbyte mod...

Page 473: ...de 64 Kbyte mode 22 14 SCALL 1 Mbyte mode 64 Kbyte mode 18 13 TRAP 1 Mbyte mode 64 Kbyte mode 25 18 Table A 9 Instruction Execution Times in State Times Continued NOTE The column entitled Reg lists th...

Page 474: ...not taken 8 jump taken JST 4 jump not taken 8 jump taken JV 4 jump not taken 8 jump taken JVT 4 jump not taken 8 jump taken Shift Mnemonic Direct NORML 8 1 per shift 9 for 0 shift SHL 6 1 per shift 7...

Page 475: ...Indirect Indexed Normal Autoinc Short Long DPTS 2 EPTS 2 Table A 9 Instruction Execution Times in State Times Continued NOTE The column entitled Reg lists the instruction execution times for accesses...

Page 476: ...B Signal Descriptions...

Page 477: ......

Page 478: ...UNCTIONAL GROUPINGS OF SIGNALS Table B 2 lists the signals for the 8XC196NT grouped by function A diagram of each package that is currently available shows the pin location of each signal NOTE As new...

Page 479: ...T2CLK PACT BREQ P1 1 EPA1 Processor Control PALE BUSWIDTH P1 2 EPA2 T2DIR EA PBUS 15 0 CLKOUT P1 7 3 EPA7 3 EXTINT PMODE 3 0 HOLD P2 0 TXD NMI PROG HLDA P2 1 RXD ONCE PVER INST P2 7 2 RESET INTOUT P3...

Page 480: ...ORT 1 A16 EPORT 0 AD15 P4 7 PBUS 15 AD14 P4 6 PBUS 14 AD13 P4 5 PBUS 13 AD12 P4 4 PBUS 12 AD11 P4 3 PBUS 11 AD10 P4 2 PBUS 10 AD9 P4 1 PBUS 9 AD8 P4 0 PBUS 8 AD7 P3 7 PBUS 7 SLP7 AD6 P3 6 PBUS 6 SLP6...

Page 481: ...nded addressing of the 1 Mbyte address space NOTE Internally there are 24 address bits however only 20 address lines A19 16 and AD15 0 are bonded out The internal address space is 16 Mbytes 000000 FFF...

Page 482: ...igh output signal is asserted only during external memory cycles ALE signals the start of an external bus cycle and indicates that valid address information is available on the system address data bus...

Page 483: ...y EPA Compare Pins These signals are the output of the EPA compare only channels These pins are multiplexed with other signals and may be configured as standard I O COMP1 0 are multiplexed as follows...

Page 484: ...n powerdown mode asserting EXTINT causes the chip to return to normal operating mode If EXTINT is enabled the EXTINT service routine is executed Otherwise execution continues at the instruction follow...

Page 485: ...IDLPD instruction that put the device into idle mode In powerdown mode a rising edge on the NMI pin does not cause the device to exit powerdown ONCE I On circuit Emulation Holding ONCE low during the...

Page 486: ...7 0 are multiplexed with AD15 8 and PBUS15 8 P5 7 0 I O Port 5 This is an 8 bit bidirectional memory mapped I O port P5 4 is multiplexed with a special test mode entry function If this pin is held low...

Page 487: ...ta on the PBUS and begins programming while a rising edge ends programming The current location is programmed with the same data as long as PROG remains asserted so the data on the PBUS must remain st...

Page 488: ...dress data bus in multiplexed mode and slave port data bus in demultiplexed mode In multiplexed mode SLP1 is the source of the internal control signal SLP_ADDR SLP7 0 are multiplexed with AD7 0 P3 7 0...

Page 489: ...th T2CLK for quadrature counting mode T2DIR is multiplexed with P1 2 and EPA2 TXD O Transmit Serial Data In serial I O modes 1 2 and 3 TXD transmits serial port output data In mode 0 it is the serial...

Page 490: ...0 CCR0 determines whether this pin functions as WR or WRL CCR0 2 1 selects WR CCR0 2 0 selects WRL During 16 bit bus cycles this active low output signal is asserted for low byte writes and word writ...

Page 491: ...ance strongly driven high ODIO Open drain I O Table B 6 8XC196NT Pin Status Port Pins Multiplexed With Status During Reset Status During Idle Status During Powerdown P0 7 4 ACH7 4 HiZ HiZ HiZ P1 7 0 E...

Page 492: ...P5 5 is LoZ1 If P5_MODE x 1 and HLDA 0 port is HiZ 2 If P5_MODE x 0 port is as programmed If P5_MODE x 1 port is HiZ 3 If Px_MODE x 0 port is as programmed If Px_MODE x 1 pin is as specified by Px_DIR...

Page 493: ......

Page 494: ...C Registers...

Page 495: ......

Page 496: ...ed Registers A D Converter Chip Configuration CPU EPA AD_COMMAND CCR0 ONES_REG COMPx_CON x 0 1 AD_RESULT CCR1 PSW COMPx_TIME x 0 1 AD_TEST CCR2 SP EPA_MASK AD_TIME PPW or SP_PPW ZERO_REG EPA_MASK1 USF...

Page 497: ...Data Output 1FE5H 0000 0000 EPA_MASK EPA Mask 1FA0H 0000 0000 0000 0000 EPA_MASK1 EPA Mask 1 1FA4H 0000 0000 EPA_PEND EPA Pending 1FA2H 0000 0000 0000 0000 EPA_PEND1 EPA Pending 1 1FA6H 0000 0000 EPA...

Page 498: ...P1_DIR Port 1 I O Direction 1FD2H 1111 1111 P1_MODE Port 1 Mode 1FD0H 0000 0000 P1_PIN Port 1 Pin Input 1FD6H XXXX XXXX P1_REG Port 1 Data Output 1FD4H 1111 1111 P2_DIR Port 2 I O Direction 1FCBH 0111...

Page 499: ...Control 1FBBH 1100 0000 SP_STATUS Serial Port Status 1FB9H 0000 1000 SSIO_BAUD Syn Serial Port Baud Rate 1FB4H 0XXX XXXX SSIO0_BUF Syn Serial Port 0 Buffer 1FB0H 0000 0000 SSIO0_CON Syn Serial Port 0...

Page 500: ...Note 2 Writing this bit arms the A D converter The value that you write to it determines at what point a conversion is to start 1 start immediately 0 EPA initiates conversion 2 0 ACH2 0 A D Channel Se...

Page 501: ...8 ADRLT9 ADRLT8 ADRLT7 ADRLT6 ADRLT5 ADRLT4 ADRLT3 ADRLT2 7 0 ADRLT1 ADRLT0 STATUS ACH2 ACH1 ACH0 Bit Number Bit Mnemonic Function 15 6 ADRLT9 0 A D Result These bits contain the A D conversion result...

Page 502: ...Voltage These bits specify the threshold value This selects a reference voltage which is compared with an analog input pin When the voltage on the analog input pin crosses over detect high or under de...

Page 503: ...y with future devices write zeros to these bits 3 2 OFF1 0 Offset These bits allows you to set the zero offset point OFF1 OFF0 0 0 no adjustment 0 1 add 2 5 mV 1 0 subtract 2 5 mV 1 1 subtract 5 0 mV...

Page 504: ...z 4 0 CONV4 0 A D Convert Time These bits specify the conversion time Use the following formula to compute the conversion time where CONV 2 to 31 TCONV the conversion time in sec from the data sheet F...

Page 505: ...ady Control These two bits along with IRC2 CCR1 1 limit the number of wait states that can be inserted while the READY pin is held low Wait states are inserted into the bus cycle either until the READ...

Page 506: ...o enter powerdown mode Clearing this bit at reset can prevent accidental entry into powerdown mode 1 enable powerdown mode 0 disable powerdown mode CCR0 Continued Address Reset State FF2018H XXH The c...

Page 507: ...ice operation write one to this bit 3 WDE Watchdog Timer Enable Selects whether the watchdog timer is always enabled or enabled the first time it is cleared 1 enabled first time it is cleared 0 always...

Page 508: ...e FFH only This register is loaded from CCB2 or PCCB2 if the LDCCB2 bit bit 0 of CCR1 is set otherwise it is loaded with FFH 7 0 REMAP MODE64 Bit Number Bit Mnemonic Function 7 3 Reserved always write...

Page 509: ...me register 6 CE Compare Enable This bit enables the compare function 0 compare function disabled 1 compare function enabled 5 4 M1 0 EPA Mode Select Specifies the type of compare event M1 M0 0 0 no o...

Page 510: ...opposite timer 0 RT Reset Timer This bit controls whether the timer selected by the ROT bit will be reset 1 resets the timer selected by the ROT bit 0 disables the reset function Table C 3 COMPx_CON A...

Page 511: ...cally to the EPAx_TIME registers The EPA triggers a compare event when the reference timer matches the value in COMPx_TIME 15 8 EPA Event Time Value high byte 7 0 EPA Event Time Value low byte Bit Num...

Page 512: ...To use an open drain output configuration an external pull up is required To use a high impedance input configu ration the corresponding bit in EP_REG must be set 7 0 PIN3 PIN2 PIN1 PIN0 Bit Number B...

Page 513: ...ther the corresponding pin functions as a standard I O port pin or is used as an extended address port EPORT pin 7 0 PIN3 PIN2 PIN1 PIN0 Bit Number Bit Mnemonic Function 7 4 Reserved always write as z...

Page 514: ...t EP_PIN register contains the current state of each port pin regardless of the pin mode setting 7 0 PIN3 PIN2 PIN1 PIN0 Bit Number Bit Mnemonic Function 7 4 Reserved always write as zeros 3 0 PIN3 0...

Page 515: ...mory page page 00H 0FH that is to be accessed by non extended instruc tions into the EP_REG x bits 7 0 PIN3 PIN2 PIN1 PIN0 Bit Number Bit Mnemonic Function 7 4 Reserved always write as zeros 3 0 PIN3...

Page 516: ...the multiplexed EPAx interrupt 15 8 EPA4 EPA5 EPA6 EPA7 EPA8 EPA9 OVR0 OVR1 7 0 OVR2 OVR3 OVR4 OVR5 OVR6 OVR7 OVR8 OVR9 Bit Number Function 15 10 Setting this bit enables the corresponding interrupt a...

Page 517: ...the multiplexed EPAx interrupt 7 0 COMP0 COMP1 OVRTM1 OVRTM2 Bit Number Function 7 4 Reserved for compatibility with future devices write zeros to these bits 3 0 Setting a bit enables the correspondi...

Page 518: ...identifies the highest priority active multiplexed interrupt source When EPAIPV is read the EPA interrupt pending bit associated with the EPAIPV priority value is cleared 15 8 EPA4 EPA5 EPA6 EPA7 EPA8...

Page 519: ...ins a number that identifies the highest priority active multiplexed interrupt source When EPAIPV is read the EPA interrupt pending bit associated with the EPAIPV priority value is cleared 7 0 COMP0 C...

Page 520: ...utput pin EPA1 with EPA capture compare channel 1 When the remap feature of EPA3 is enabled EPA capture compare channel 2 shares output pin EPA3 with EPA capture compare channel 3 0 remap feature disa...

Page 521: ...nt 1 compare function always enabled 2 AD A D Conversion Allows the EPA to start an A D conversion that has been previously set up in the A D control registers To use this feature you must select the...

Page 522: ...E and its buffer are both full When an overrun occurs the ON bit determines whether old data is overwritten or new data is ignored 0 ignores new data 1 overwrites old data in the buffer In Compare Mod...

Page 523: ...nd Reset Values Register Address Reset Value Register Address Reset Value EPA0_CON 1F60H 00H EPA5_CON 1F74H 00H EPA1_CON 1F64H FE00H EPA6_CON 1F78H 00H EPA2_CON 1F68H 00H EPA7_CON 1F7CH 00H EPA3_CON 1...

Page 524: ...for compare mode 15 8 EPA Timer Value high byte 7 0 EPA Timer Value low byte Bit Number Function 15 0 EPA Time Value When an EPA channel is configured for capture mode this register contains the value...

Page 525: ...EPA pending bits are cleared the EPAx pending bit is also cleared 7 0 PV4 PV3 PV2 PV1 PV0 Bit Number Bit Mnemonic Function 5 7 Reserved always write as zeros 4 0 PV4 0 Priority Vector These bits cont...

Page 526: ...monic Interrupt Standard Vector IBF Slave Port Input Buffer Full FF200EH OBE Slave Port Output Buffer Empty FF200CH AD A D Conversion Complete FF200AH EPA0 EPA Capture Compare Channel 0 FF2008H EPA1 E...

Page 527: ...register on the stack and POPA restores it 7 0 NMI EXTINT RI TI SSIO1 SSIO0 CBF Bit Number Function 7 6 4 0 Setting a bit enables the corresponding interrupt The standard interrupt vector locations ar...

Page 528: ...ndard interrupt vector locations are as follows Bit Mnemonic Interrupt Standard Vector IBF Slave Port Input Buffer Full FF200EH OBE Slave Port Output Buffer Empty FF200CH AD A D Conversion Complete FF...

Page 529: ...NMI EXTINT RI TI SSIO1 SSIO0 CBF Bit Number Function 7 6 4 0 Any set bit indicates that the corresponding interrupt is pending The interrupt bit is cleared when processing transfers to the correspond...

Page 530: ...y bit contains the complement of the EA pin which controls whether accesses to locations FF2000 FF9FFFH are directed to the internal OTPROM or to external memory 1 the EA pin is active accesses are di...

Page 531: ...Reset State 02H FFFFH The two byte ones register ONES_REG is always equal to FFFFH It is useful as a fixed source of all ones for comparison operations 15 8 One high byte 7 0 One low byte Bit Number F...

Page 532: ...nput are identical An open drain output configuration requires an external pull up A high impedance input configuration requires that the corresponding bit in Px_REG be set 7 0 x 1 2 5 6 PIN7 PIN6 PIN...

Page 533: ...n signal 7 0 x 1 2 5 6 PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0 Bit Number Bit Mnemonic Function 7 0 PIN7 0 Port x Pin y Mode This bit determines the mode of the corresponding port pin 0 standard I O p...

Page 534: ...2 2 EXTINT PROG P1 3 EPA3 P2 3 BREQ P1 4 EPA4 P2 4 INTOUT AINC P1 5 EPA5 P2 5 HOLD P1 6 EPA6 P2 6 HLDA ONCE CPVER P1 7 EPA7 P2 7 CLKOUT PACT Port 5 Port 6 Pin Special function Signal Pin Special funct...

Page 535: ...he pin mode setting 7 0 x 0 6 PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0 Bit Number Bit Mnemonic Function 7 0 PIN7 0 Port x Pin y Input Value This bit contains the current state of Px y Table C 11 Px_PIN...

Page 536: ...when the associated pins are configured as standard I O port pins Px_MODE y 0 7 0 x 1 6 PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0 Bit Number Bit Mnemonic Function 7 0 PIN7 0 Port x Pin y Output To use...

Page 537: ...ode does not require ports 3 and 4 to be externally pulled high by pull up resistors 7 0 P3DRV P4DRV Bit Number Bit Mnemonic Function 7 P3DRV Port 3 I O Mode This bit controls whether port 3 is config...

Page 538: ...h which must be at least 100 s for successful programming 15 8 1 PPW14 PPW13 PPW12 PPW11 PPW10 PPW9 PPW8 7 0 PPW7 PPW6 PPW5 PPW4 PPW3 PPW2 PPW1 PPW0 Bit Number Bit Mnemonic Function 15 1 Set this bit...

Page 539: ...nsures that the zero flag will reflect the result of the entire operation not just the last calculation For example if the result of adding together the lower words of two double words is zero the zer...

Page 540: ...K and INT_MASK1 individually enable or disable the interrupts The EI instruction sets this bit DI clears it 1 enable interrupt servicing 0 disable interrupt servicing 0 ST Sticky Bit Flag This flag is...

Page 541: ...s write zero to this bit 14 12 0 Setting a bit causes the corresponding interrupt to be handled by a PTS microcode routine The PTS interrupt vector locations are as follows Bit Mnemonic Interrupt PTS...

Page 542: ...it is set by hardware to request an end of PTS interrupt for the corresponding interrupt through its standard interrupt vector The standard interrupt vector locations are as follows Bit Mnemonic Inter...

Page 543: ...ta is held in the receive shift register until the last data bit is received then the data byte is loaded into SBUF_RX If data in the shift register is loaded into SBUF_RX before the previous byte is...

Page 544: ...that is ready for transmission In modes 1 2 and 3 writing to SBUF_TX starts a transmission In mode 0 writing to SBUF_TX starts a transmission only if the receiver is disabled SP_CON 3 0 7 0 Data to T...

Page 545: ...The commands are defined by the device software The slave can read from and write to this register The master can only write to it To write to SLP_CMD rather than P3_PIN the master must first write 1...

Page 546: ...enables the slave port 2 SLPL Slave Port Latch In standard slave mode only this bit determines the source of the internal control signal SLP_ADDR When SLP_ADDR is held high the master can write to th...

Page 547: ...hether the bus interface logic received a read 1 or a write 0 SMO can be read but not written In standard slave mode bit 7 SF4 is the high bit of the status field 6 3 SF3 0 Status Field The slave can...

Page 548: ...emented before a PUSH and incremented after a POP so the stack pointer should be initialized to two bytes in 64 Kbyte mode or four bytes in 1 Mbyte mode above the highest stack location If stack opera...

Page 549: ...02H for receptions 15 8 CLKSRC BV14 BV13 BV12 BV11 BV10 BV9 BV8 7 0 BV7 BV6 BV5 BV4 BV3 BV2 BV1 BV0 Bit Number Bit Mnemonic Function 15 CLKSRC Serial Port Clock Source This bit determines whether the...

Page 550: ..._CON 2 is set this bit takes on the even parity value 3 REN Receive Enable Setting this bit enables the receiver function of the RXD pin When this bit is set a high to low transition on the pin starts...

Page 551: ...st data bit is sampled Reading SP_STATUS clears this bit This bit need not be clear for the serial port to receive data 5 TI Transmit Interrupt This bit is set at the beginning of the stop bit transmi...

Page 552: ...lear BV6 0 1 enable the baud rate generator and start the down counter For read operations 0 baud rate generator is disabled 1 baud rate generator is enabled and down counter is running 6 0 BV6 0 Baud...

Page 553: ...for transmission Data is shifted from this register to the SDx pin with the most significant bit first 7 0 RXD Data Received 7 0 TXD Data to Transmit Bit Number Function 7 0 Data Received During recep...

Page 554: ...ransfer 0 do not switch 1 switch toggle T R and clear TRT at the end of the current transfer Setting TRT allows the channel configuration to change immediately on transfer completions thus avoiding po...

Page 555: ...SSIOx_BUF For the transmitter T R 1 0 SSIOx_BUF is full waiting to transmit 1 SSIOx_BUF is empty buffer available For the receiver T R 0 0 SSIOx_BUF is empty waiting to receive 1 SSIOx_BUF is full da...

Page 556: ...ock Direction Mode Bits These bits determine the timer clocking source and direction control source M2 M1 M0 Clock Source Direction Source 0 0 0 FOSC 4 UD bit T1CONTROL 6 X 0 1 T1CLK Pin UD bit T1CONT...

Page 557: ...hese bits determine the timer clocking source and direction source M2 M1 M0 Clock Source Direction Source 0 0 0 FOSC 4 UD bit T2CONTROL 6 X 0 1 T2CLK Pin UD bit T2CONTROL 6 0 1 0 FOSC 4 T2DIR Pin 0 1...

Page 558: ...tten allowing timer x to be initialized to a value other than zero 15 8 Timer Value high byte 7 0 Timer Value low byte Bit Number Function 15 0 Timer Read the current timer x value from this register...

Page 559: ...for failure analysis 7 0 DEI DED OFD Bit Number Bit Mnemonic Function 7 4 Reserved always write as zeros 3 DEI Disable External Instruction Fetch Setting this bit prevents the bus controller from exec...

Page 560: ...fter it is enabled the watchdog can be disabled only by a reset The WDE bit bit 3 of CCR1 controls whether the watchdog is enabled immediately or is disabled until the first time it is cleared Clearin...

Page 561: ...number 6 5 4 3 2 1 0 1 x x x x x x 32 byte window W5 0 window number 0 1 x x x x x 64 byte window W4 0 window number 0 0 1 x x x x 128 byte window W3 0 window number Table C 17 WSR Settings and Direct...

Page 562: ...0FAH EPA7_CON 1F7CH 7BH 00FCH 3DH 00FCH 1EH 00FCH EPA7_TIME 1F7EH 7BH 00FEH 3DH 00FEH 1EH 00FEH EPA8_CON 1F80H 7CH 00E0H 3EH 00C0H 1FH 0080H EPA8_TIME 1F82H 7CH 00E2H 3EH 00C2H 1FH 0082H EPA9_CON 1F84...

Page 563: ...UD 1FB4H 7DH 00F4H 3EH 00F4H 1FH 00B4H SSIO0_BUF 1FB0H 7DH 00F0H 3EH 00F0H 1FH 00B0H SSIO0_CON 1FB1H 7DH 00F1H 3EH 00F1H 1FH 00B1H SSIO1_BUF 1FB2H 7DH 00F2H 3EH 00F2H 1FH 00B2H SSIO1_CON 1FB3H 7DH 00F...

Page 564: ...0000H The two byte zero register ZERO_REG is always equal to zero It is useful as a fixed source of the constant zero for comparisons and calculations 15 8 Zero high byte 7 0 Zero low byte Bit Number...

Page 565: ......

Page 566: ...Glossary...

Page 567: ......

Page 568: ...verter Analog to digital converter ALU Arithmetic logic unit The part of the RALU that processes arithmetic and logical operations assert The act of making a signal active enabled The polarity high or...

Page 569: ...nd on channel resistance from one multiplexer channel to another characteristic A graph of output code versus input voltage the transfer function of an A D converter chip select logic External circuit...

Page 570: ...sure of overall code transition error doping The process of introducing a periodic table Group III or Group V element into a Group IV element e g silicon A Group III impurity e g indium or gallium res...

Page 571: ...ld latency The time it takes the microcontroller to assert HLDA after an external device asserts HOLD ideal characteristic The characteristic of an ideal A D converter An ideal characteristic is uniqu...

Page 572: ...bit of a byte or least significant byte of a word 2 In an A D converter the reference voltage divided by 2n where n is the number of bits to be converted For a 10 bit converter with a reference voltag...

Page 573: ...s that code only Large differential nonlinearity errors can cause the converter to miss codes nonlinearity The maximum deviation of code transitions of the terminal based characteristic from the corre...

Page 574: ...maskable interrupt or nonmaskable NMI Two of the nonmaskable interrupts unimplemented opcode and software trap are not prioritized they vector directly to the interrupt service routine when executed...

Page 575: ...olled by the contents of the PTS control block PTS transfer The movement of a single byte or word from the source memory location to the destination memory location PTS vector A location in special pu...

Page 576: ...ed input channel sample delay The time period between the time that A D converter receives the start conversion signal and the time that the sample capacitor is connected to the selected channel sampl...

Page 577: ...lowing out of a device from VCC Always a negative value SP Stack pointer special interrupt Any of the three nonmaskable interrupts unimple mented opcode software trap or NMI special purpose memory A p...

Page 578: ...f the A D converter transfer function errors Errors inherent in an analog to digital conversion process quantizing error zero offset error full scale error differential nonlinearity and nonlinearity E...

Page 579: ...ress bits and directs access to the page value expressed by the lower bits zero extension A method for converting data to a larger format by filling the upper bit positions with zeros zero offset erro...

Page 580: ...Index...

Page 581: ......

Page 582: ...11 4 terminal based characteristic 11 19 threshold detection modes 11 6 transfer function 11 16 11 19 zero offset adjustment 11 3 11 5 zero offset error 11 17 See also port 0 A D scan mode See PTS A1...

Page 583: ...VI instruction A 3 A 9 A 10 A 50 A 55 BR indirect instruction A 2 A 10 A 50 A 56 A 63 BREQ 14 3 14 19 B 6 Bulletin board system BBS 1 9 Bus contention See address data bus contention Bus controller 2...

Page 584: ...A 59 CMPL instruction A 2 A 12 A 50 A 52 A 59 Code execution 2 4 2 5 Code fetches 4 26 COMP0_CON C 66 COMP0_TIME C 66 COMP1_CON C 66 COMP1_TIME C 66 CompuServe forums 1 10 Conditional jump instruction...

Page 585: ...61 C 62 determining event status 10 27 enabling a timer counter 10 18 10 19 C 61 C 62 enabling remapping for PWM 10 21 C 25 enabling the compare function 10 25 C 14 multiplexed interrupts 10 29 re ena...

Page 586: ...B 7 and powerdown mode 13 4 13 5 13 6 hardware considerations 13 7 F FaxBack service 1 8 FE opcode and inhibiting interrupts 5 8 Floating point library 3 5 Formulas A D conversion result 11 9 11 14 A...

Page 587: ...Kbyte mode Instruction set 3 1 additions 3 5 3 6 and PSW flags A 5 code execution 2 4 2 5 conventions 1 3 differences 3 5 execution times A 59 A 60 lengths A 52 A 59 opcode map A 2 A 3 opcodes A 46 A...

Page 588: ...ments defined 1 5 Memory bus 2 5 Memory configuration examples 4 28 4 33 Memory controller 2 3 2 5 Memory mapping auto programming mode 15 27 serial port programming mode 15 33 Memory modes 4 1 4 35 M...

Page 589: ...owerdown mode 13 4 detecting failure 12 9 12 12 external crystal 12 7 on chip 12 5 OTPROM controlling access to internal memory 15 3 15 6 controlling fetches from external memory 15 6 15 7 enabling os...

Page 590: ...zing 6 9 input buffer 6 6 logic tables 6 8 operation 6 3 6 8 overview 6 1 pin configuration 6 9 6 11 example 6 10 SFRs 6 5 10 4 10 5 structure 6 7 See also EPA Port 2 2 8 13 2 B 9 considerations 6 11...

Page 591: ...gramming voltages 12 1 13 2 15 13 B 12 calculating 15 15 Program word routine 15 22 PSW 2 3 3 13 5 13 C 31 flags and instructions A 5 PTS 2 3 2 5 2 6 2 10 5 1 A D scan mode 5 26 5 31 and A D converter...

Page 592: ...4 INT_PEND 5 4 5 16 11 2 INT_PEND1 5 4 5 16 7 2 8 3 8 8 9 4 9 5 naming conventions 1 4 P0_PIN 6 1 6 2 6 3 11 3 P1_MODE considerations 6 11 P2_DIR 7 2 P2_MODE 7 2 considerations 6 11 6 12 P2_PIN 7 2 8...

Page 593: ...des 1 2 and 3 7 5 S Sampled input 14 11 B 4 SBUF_RX C 68 SBUF_TX C 68 SC0 8 5 B 11 configuring for handshaking 8 6 SC1 8 5 B 11 configuring for handshaking 8 6 SCALL instruction A 3 A 35 A 46 A 52 A 5...

Page 594: ...tialization 9 14 slave program 9 9 9 12 configuring pins 9 14 determining status 9 16 hardware connections 9 6 9 7 initializing SFRs 9 14 interrupts 9 8 9 16 CBF interrupt 9 16 IBF interrupt 9 16 OBE...

Page 595: ...1DIR 10 3 B 12 T2CLK 10 3 B 12 T2CONTROL 10 5 C 68 T2DIR 10 3 B 12 Technical support 1 11 Terminology 1 3 TIJMP instruction A 2 A 43 A 50 A 56 A 63 and EPAx interrupt 10 29 10 31 Timer watchdog See wa...

Page 596: ...linker loader 4 20 table of 4 16 4 17 4 18 C 66 WORD defined 3 3 World Wide Web 1 10 WR 14 5 B 13 during bus hold 14 19 idle powerdown reset status B 14 Wraparound defined 4 2 WRH 14 3 14 5 B 13 Write...

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