Intel 8XC196NT, User Manual

Page: 130 / 597

5-25
STANDARD AND PTS INTERRUPTS
PTS Block Transfer Mode Control Block
In block transfer mode, the PTS control block contains a block size (PTSBLOCK), a source and
destination address (PTSSRC and PTSDST), a control register (PTSCON), and a transfer count
(PTSCOUNT).
7 0
Unused 0 0 0 0 0 0 0 0
7 0
PTSBLOCK PTS Block Size
15 8
PTSDST (HI) PTS Destination Address (high byte)
7 0
PTSDST (LO) PTS Destination Address (low byte)
15 8
PTSSRC (HI) PTS Source Address (high byte)
7 0
PTSSRC (LO) PTS Source Address (low byte)
7 0
PTSCON M2 M1 M0 BW SU DU SI DI
7 0
PTSCOUNT Consecutive Block Transfers
Register Location Function
PTSBLOCK PTSCB + 6 PTS Block Size
Specifies the number of bytes or words in each block. Valid values are
1–32, inclusive.
PTSDST PTSCB + 4 PTS Destination Address
Write the destination memory location to this register. A valid address is
any unreserved memory location within page 00H; however, it must
point to an even address if word transfers are selected.
PTSSRC PTSCB + 2 PTS Source Address
Write the source memory location to this register. A valid address is any
unreserved memory location within page 00H; however, it must point to
an even address if word transfers are selected.
Figure 5-13. PTS Control Block – Block Transfer Mode