Intel 8XC196NT, User Manual

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14-5
INTERFACING WITH EXTERNAL MEMORY
14.3 CHIP CONFIGURATION REGISTERS AND CHIP CONFIGURATION BYTES
Three chip configuration registers (CCRs) have bits that set parameters for chip operation and ex-
ternal bus cycles. The CCRs cannot be accessed by code. They are loaded from the chip config-
uration bytes (CCBs), which have internal addresses FF2018H (CCB0), FF201AH (CCB1), and
FF201C (CCB2). If the CCBs are stored in external memory, their external addresses depend on
the number of EPORT lines used in the external system (see “Internal and External Addresses”
on page 14-1).
When the device returns from reset, the bus controller fetches the CCBs and loads them into the
CCRs. From this point, these CCR bit values define the chip configuration until the device is reset
again. The CCR bits are described in Figures 14-1 through 14-3.
READY I Ready Input
This active-high input signal is used to lengthen external memory
cycles for slow memory by generating wait states in addition to the
wait states that are generated internally.
When READY is high, CPU operation continues in a normal manner
with wait states inserted as programmed in the chip configuration
registers. READY is ignored for all internal memory accesses.
P5.6
WR# O Write
The chip configuration register 0 (CCR0) determines whether this pin
functions as WR# or WRL#. CCR0.2=1 selects WR#; CCR0.2=0
selects WRL#.
This active-low output indicates that an external write is occurring.
This signal is asserted only during external memory writes.
P5.2/WRL#/
SLPWR#
WRH# O Write High
The chip configuration register 0 (CCR0) determines whether this pin
functions as BHE# or WRH#. CCR0.2=1 selects BHE; CCR0.2=0
selects WRH#.
During 16-bit bus cycles, this active-low output signal is asserted for
high-byte writes and word writes to external memory. During 8-bit
bus cycles, WRH# is asserted for all write operations.
P5.5/BHE#
WRL# O Write Low
The chip configuration register 0 (CCR0) determines whether this pin
functions as WR# or WRL#. CCR0.2=1 selects WR#; CCR0.2=0
selects WRL#.
During 16-bit bus cycles, this active-low output signal is asserted for
low-byte writes and word writes. During 8-bit bus cycles, WRL# is
asserted for all write operations.
P5.2/WR#/S
LPWR#
Table 14-2. External Memory Interface Signals (Continued)
Function
Name
Type Description
Multiplexed
With