Intel 8XC196NT, User Manual

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14-19
INTERFACING WITH EXTERNAL MEMORY
Figure 14-8. READY Timing Diagram
14.6 BUS-HOLD PROTOCOL
The device supports a bus-hold protocol that allows external devices to gain control of the ad-
dress/data bus. The protocol uses three signals, all of which are port 2 special functions:
HOLD#/P2.5 (hold request), HLDA#/P2.6 (hold acknowledge), and BREQ#/P2.3 (bus request).
When an external device wants to use the device bus, it asserts the HOLD# signal. HOLD# is
sampled while CLKOUT is low. The device responds by releasing the bus and asserting HLDA#.
During this hold time, the address/data bus floats, and signals ALE, RD#, WR#/WRL#,
BHE#/WRH#, and INST are weakly held in their inactive states. Figure 14-9 shows the timing
for bus-hold protocol, and Table 14-4 on page 14-20 lists the timing parameters and their defini-
tions. Refer to the data sheet for timing parameter values.
T
AVYV
T
CLYX
(MIN)
T
CLYX
(MAX)
Address Out Data Out
Address Out Data
Address
AD15:0
WR#
AD15:0
RD#
READY
ALE
CLKOUT
Extended Address Out A19:16
A0283-02