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A-27
INSTRUCTION SET REFERENCE
JVT
JUMP IF OVERFLOW-TRAP FLAG IS SET.
Tests the overflow-trap flag. If the flag is clear,
control passes to the next sequential
instruction. If the overflow-trap flag is set, this
instruction clears the flag and adds to the
program counter the offset between the end
of this instruction and the target label,
effecting the jump. The offset must be in
range of –128 to +127.
if VT = 1 then
PC
←
PC + 8-bit disp
JVT cadd
(11011100) (disp)
NOTE:
The displacement (disp) is sign-
extended to 24 bits.
PSW Flag Settings
Z
N
C
V
VT
ST
—
—
—
—
0
—
LCALL
LONG CALL. Pushes the contents of the
program counter (the return address) onto
the stack, then adds to the program counter
the offset between the end of this instruction
and the target label, effecting the call. The
offset must be in the range of –32,768 to
+32,767.
64-Kbyte mode:
SP
←
SP – 2
(SP)
←
PC
PC
←
PC + 16-bit disp
1-Mbyte mode:
SP
←
SP – 4
(SP)
←
PC
PC
←
PC + 24-bit disp
LCALL cadd
(11101111) (disp-low) (disp-high)
NOTE:
The displacement (disp) is sign-
extended to 24 bits in the 1-Mbyte
addressing mode. This displace-
ment may cause the program
counter to cross a page boundary.
PSW Flag Settings
Z
N
C
V
VT
ST
—
—
—
—
—
—
LD
LOAD WORD. Loads the value of the source
word operand into the destination operand.
(DEST)
←
(SRC)
DEST, SRC
LD
wreg, waop
(101000aa) (waop) (wreg)
PSW Flag Settings
Z
N
C
V
VT
ST
—
—
—
—
—
—
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
Summary of Contents for 8XC196NT
Page 1: ...8XC196NT Microcontroller User s Manual...
Page 2: ...8XC196NT Microcontroller User s Manual June 1995 Order Number 272317 003...
Page 22: ...1 Guide to This Manual...
Page 23: ......
Page 35: ......
Page 36: ...2 Architectural Overview...
Page 37: ......
Page 49: ......
Page 50: ...3 Programming Considerations...
Page 51: ......
Page 66: ...4 Memory Partitions...
Page 67: ......
Page 104: ...5 Standard and PTS Interrupts...
Page 105: ......
Page 147: ......
Page 148: ...6 I O Ports...
Page 149: ......
Page 176: ...7 Serial I O SIO Port...
Page 177: ......
Page 194: ...8 Synchronous Serial I O SSIO Port...
Page 195: ......
Page 211: ......
Page 212: ...9 Slave Port...
Page 213: ......
Page 231: ......
Page 232: ...10 Event Processor Array EPA...
Page 233: ......
Page 270: ...11 Analog to digital Converter...
Page 271: ......
Page 291: ......
Page 292: ...12 Minimum Hardware Considerations...
Page 293: ......
Page 306: ...13 Special Operating Modes...
Page 307: ......
Page 317: ......
Page 318: ...14 Interfacing with External Memory...
Page 319: ......
Page 362: ...15 Programming the Nonvolatile Memory...
Page 363: ......
Page 408: ...A Instruction Set Reference...
Page 409: ......
Page 476: ...B Signal Descriptions...
Page 477: ......
Page 493: ......
Page 494: ...C Registers...
Page 495: ......
Page 565: ......
Page 566: ...Glossary...
Page 567: ......
Page 580: ...Index...
Page 581: ......
Page 597: ......