8XC196NT USER’S MANUAL
Glossary-2
CCBs
Chip configuration bytes. The chip configuration
registers (CCRs) are loaded with the contents of the
CCBs after a device reset, unless the device is
entering programming modes, in which case the
PCCBs is used.
CCRs
Chip configuration registers. Registers that specify
the environment in which the device will be
operating. The chip configuration registers are loaded
with the contents of the CCBs after a device reset
unless the device is entering programming modes, in
which case the PCCBs are used.
channel-to-channel matching error
The difference between corresponding code
transitions of actual characteristics taken from
different A/D converter channels under the same
temperature, voltage, and frequency conditions. This
error is caused by differences in DC input leakage and
on-channel resistance from one multiplexer channel
to another.
characteristic
A graph of output code versus input voltage; the
transfer function of an A/D converter.
chip-select logic
External circuitry that selects a memory device during
an external bus cycle.
clear
The “0” value of a bit or the act of giving it a “0”
value. See also set.
code
1) A set of instructions that perform a specific
function; a program.
2) The digital value output by the A/D converter.
code center
The voltage corresponding to the midpoint between
two adjacent code transitions on the A/D converter.
code transition
The point at which the A/D converter’s output code
changes from “Q” to “Q+1.” The input voltage corre-
sponding to a code transition is defined as the voltage
that is equally likely to produce either of two adjacent
codes.
code width
The voltage change corresponding to the difference
between two adjacent code transitions. Code width
deviations cause differential nonlinearity and nonlin-
earity errors.
crosstalk See
off-isolation.
Summary of Contents for 8XC196NT
Page 1: ...8XC196NT Microcontroller User s Manual...
Page 2: ...8XC196NT Microcontroller User s Manual June 1995 Order Number 272317 003...
Page 22: ...1 Guide to This Manual...
Page 23: ......
Page 35: ......
Page 36: ...2 Architectural Overview...
Page 37: ......
Page 49: ......
Page 50: ...3 Programming Considerations...
Page 51: ......
Page 66: ...4 Memory Partitions...
Page 67: ......
Page 104: ...5 Standard and PTS Interrupts...
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Page 147: ......
Page 148: ...6 I O Ports...
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Page 176: ...7 Serial I O SIO Port...
Page 177: ......
Page 194: ...8 Synchronous Serial I O SSIO Port...
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Page 211: ......
Page 212: ...9 Slave Port...
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Page 231: ......
Page 232: ...10 Event Processor Array EPA...
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Page 270: ...11 Analog to digital Converter...
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Page 292: ...12 Minimum Hardware Considerations...
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Page 306: ...13 Special Operating Modes...
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Page 317: ......
Page 318: ...14 Interfacing with External Memory...
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Page 362: ...15 Programming the Nonvolatile Memory...
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Page 408: ...A Instruction Set Reference...
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Page 476: ...B Signal Descriptions...
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Page 493: ......
Page 494: ...C Registers...
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Page 566: ...Glossary...
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Page 580: ...Index...
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