Intel 8XC196NT, User Manual

Page: 226 / 597

9-13
SLAVE PORT
9.4.2.3 Multiplexed Bus Timings
The memory space required for the sample code is four bytes (two bytes for the address register,
one for the temp register, and one for the base address). Reads and writes each require 58 state
times (5.8 µs at 20 MHz). These times do not include interrupt latency (see “Interrupt Latency”
on page 5-7). They also do not include the master device bus cycle time. Each read or write op-
eration requires only one master bus cycle. Figure 9-5 shows relative timing relationships. Con-
sult the datasheet for actual timing specifications.
Figure 9-5. Standard or Shared Memory Mode Timings (Multiplexed Bus)
A0306-03
SLPCS#
SLPALE
(Note 1)
SLPRD#
SLP7:0/
P3.7:0
SLPWR#
SLPINT
(Note 2)
Notes:
1. Connect to master's ALE signal.
2. The falling edge of SLPINT is the same for both standard and PTS interrupts. It follows the falling
edge of SLPALE when SLPCS# is low. However, the rising edge of SLPINT occurs earlier for PTS
interrupts than for standard.
3. Rising edge associated with either
– Read ready (write to P3_REG)
– Write complete (read of P3_PIN)
Data Address
(Note 3)