![Intel 8XC196NT User Manual Download Page 284](http://html1.mh-extra.com/html/intel/8xc196nt/8xc196nt_user-manual_2072210284.webp)
11-13
ANALOG-TO-DIGITAL CONVERTER
11.6.1.2
Suggested A/D Input Circuit
The suggested A/D input circuit shown in Figure 11-8 provides limited protection against over-
voltage conditions on the analog input. Should the input voltage be driven significantly below
ANGND or above V
REF
, diode D2 or D1 will forward bias at about 0.8 volts. The device’s input
protection begins to turn on at approximately 0.5 volts beyond ANGND or V
REF
. The 270
Ω
re-
sistor limits the current input to the analog input pin to a safe value, less than 1 mA.
NOTE
Driving any analog input more than 0.5 volts beyond ANGND or V
REF
begins
to activate the input protection devices. This drives current into the internal
reference circuitry and substantially degrades the accuracy of A/D conversions
on all channels.
Figure 11-8. Suggested A/D Input Circuit
11.6.1.3
Analog Ground and Reference Voltages
Reference supply levels strongly influence the absolute accuracy of the conversion. For this rea-
son, we recommend that you tie the ANGND pin to the V
SS
pin as close to the device as possible,
using a minimum trace length. In a noisy environment, we highly recommend the use of a sepa-
rate analog ground plane that connects to V
SS
at a single point as close to the device as possible.
I
REF
may vary between 2 mA and 5 mA during a conversion. To minimize the effect of this fluc-
tuation, mount a 1.0 µF ceramic or tantalum bypass capacitor between V
REF
and ANGND, as
close to the device as possible.
ACH
x
ANGND
(Optional)
D1
D2
270
Ω
100
Ω
0.005µF
ANGND
A0082-03
V
REF
V
REF
8XC196
Device
Summary of Contents for 8XC196NT
Page 1: ...8XC196NT Microcontroller User s Manual...
Page 2: ...8XC196NT Microcontroller User s Manual June 1995 Order Number 272317 003...
Page 22: ...1 Guide to This Manual...
Page 23: ......
Page 35: ......
Page 36: ...2 Architectural Overview...
Page 37: ......
Page 49: ......
Page 50: ...3 Programming Considerations...
Page 51: ......
Page 66: ...4 Memory Partitions...
Page 67: ......
Page 104: ...5 Standard and PTS Interrupts...
Page 105: ......
Page 147: ......
Page 148: ...6 I O Ports...
Page 149: ......
Page 176: ...7 Serial I O SIO Port...
Page 177: ......
Page 194: ...8 Synchronous Serial I O SSIO Port...
Page 195: ......
Page 211: ......
Page 212: ...9 Slave Port...
Page 213: ......
Page 231: ......
Page 232: ...10 Event Processor Array EPA...
Page 233: ......
Page 270: ...11 Analog to digital Converter...
Page 271: ......
Page 291: ......
Page 292: ...12 Minimum Hardware Considerations...
Page 293: ......
Page 306: ...13 Special Operating Modes...
Page 307: ......
Page 317: ......
Page 318: ...14 Interfacing with External Memory...
Page 319: ......
Page 362: ...15 Programming the Nonvolatile Memory...
Page 363: ......
Page 408: ...A Instruction Set Reference...
Page 409: ......
Page 476: ...B Signal Descriptions...
Page 477: ......
Page 493: ......
Page 494: ...C Registers...
Page 495: ......
Page 565: ......
Page 566: ...Glossary...
Page 567: ......
Page 580: ...Index...
Page 581: ......
Page 597: ......