Intel 8XC196NT, User Manual

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8XC196NT USER’S MANUAL
6-12
P2.6/HLDA# The HLDA# pin is used in systems with more than one processor
using the system bus. This device asserts HLDA# to indicate that it
has freed the bus in response to HOLD# and another processor can
take control. (This signal is active low to avoid misinterpretation by
external hardware immediately after reset.)
P2.6/HLDA# is the enable pin for ONCE mode (see Chapter 13,
“Special Operating Modes”) and one of the enable pins for Intel-
reserved test modes. Because a low input during reset could cause the
device to enter ONCE mode or a reserved test mode, exercise
caution if you use this pin for input. Be certain that your system
meets the V
IH
specification (listed in the datasheet) during reset to
prevent inadvertent entry into ONCE mode or a test mode.
P2.7/CLKOUT Following reset, P2.7 carries the strongly driven CLKOUT signal. It
is not held high. When P2.7 is configured as CLKOUT, it is always a
complementary output.
P2.7 A value written to P2_REG.7 is held in a buffer until P2_MODE.7 is
cleared, at which time the value is loaded into P2_REG.7. A value
read from P2_REG.7 is the value currently in the register, not the
value in the buffer. Therefore, any change to P2_REG.7 can be read
only after P2_MODE.7 is cleared.
Port 5 After reset, the device configures port 5 to match the external system.
The following paragraphs describe the states of the port 5 pins after
reset and until your software writes to the P5_MODE register.
Writing to P5_MODE not only configures the pins but also turns off
the transistor that weakly holds the pins high (Q4 in Figure 6-2 on
page 6-7). For this reason, even if port 5 is to be used as it is
configured at reset, you should still write data into P5_MODE.
P5.0/ALE If EA# is high on reset (internal access), the pin is weakly held high
until your software writes to P5_MODE. If EA# is low on reset
(external access), either ALE or ADV# is activated as a system
control pin, depending on the ALE bit of CCR0. In either case, the
pin becomes a true complementary output.
P5.1/INST This pin remains weakly held high until your software writes config-
uration data into P5_MODE.
P5.2/WR#/WRL# This pin remains weakly held high until your software writes config-
uration data into P5_MODE.
P5.3/RD# If EA# is high on reset (internal access), the pin is weakly held high
until your software writes to P5_MODE. If EA# is low on reset
(external access), RD# is activated as a system control pin and the
pin becomes a true complementary output.