Intel 8XC196NT, User Manual

Page: 108 / 597

5-3
STANDARD AND PTS INTERRUPTS
Figure 5-1 illustrates the interrupt processing flow. In this flow diagram, “INT_MASK” repre-
sents both the INT_MASK and INT_MASK1 registers, and “INT_PEND” represents both the
INT_PEND and INT_PEND1 registers.
5.2 INTERRUPT SIGNALS AND REGISTERS
Table 5-1 describes the external interrupt signals and Table 5-2 describes the control and status
registers for both the interrupt controller and PTS.
Table 5-1. Interrupt Signals
PWM Signal Port Pin Type Description
EXTINT P2.2 I External Interrupt
In normal operating mode, a rising edge on EXTINT sets the
EXTINT interrupt pending bit. EXTINT is sampled during
phase 2 (CLKOUT high). The minimum high time is one state
time.
If the chip is in idle mode and if EXTINT is enabled, a rising
edge on EXTINT brings the chip back to normal operation,
where the first action is to execute the EXTINT service
routine. After completion of the service routine, execution
resumes at the the IDLPD instruction following the one that
put the device into idle mode.
In powerdown mode, asserting EXTINT causes the device to
return to normal operating mode. If EXTINT is enabled, the
EXTINT service routine is executed. Otherwise, execution
continues at the instruction following the IDLPD instruction
that put the device into powerdown mode.
NMI — I Nonmaskable Interrupt
In normal operating mode, a rising edge on NMI causes a
vector through the NMI interrupt at location FF203EH. NMI
must be asserted for greater than one state time to guarantee
that it is recognized.
In idle mode, a rising edge on the NMI pin causes the device
to return to normal operation, where the first action is to
execute the NMI service routine. After completion of the
service routine, execution resumes at the instruction following
the IDLPD instruction that put the device into idle mode.
In powerdown mode, a rising edge on the NMI pin does not
cause the device to exit powerdown.
Table 5-2. Interrupt and PTS Control and Status Registers
Mnemonic Address Description
EPA_MASK
EPA_MASK1
1FA0H, 1FA1H
1FA4H
EPA Interrupt Mask Registers
These registers enable/disable the 20 multiplexed EPA interrupts.