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6-21
I/O PORTS
Figure 6-5 shows a circuit schematic for a single bit of the EPORT. Q1 and Q2 are the strong com-
plementary drivers for the pin. Q1
can source at least –3 mA at V
CC
– 0.7 volts. Q2 can sink at
least 3 mA at 0.45 volts. (Consult the datasheet for specifications.) Resistor R1 provides ESD pro-
tection for the pin.
6.5.1.1
Reset
During reset, the falling edge of RESET# generates a short pulse that turns on the medium pull-
up transistor Q3, which remains on for about 300 ns, causing the pin to change rapidly to its reset
state. The active-low level of RESET# turns on transistor Q4, which weakly holds the pin high.
(Q4 can source approximately –10
µΑ;
consult the datasheet for exact specifications.) When RE-
SET# is inactive, both Q3 and Q4 are off; Q1 and Q2 determine output drive.
6.5.1.2
Output Enable
If RESET#, HOLD#, IDLE, or POWERDOWN is asserted, the gates that control Q1 and Q2 are
disabled and Q1 and Q2 remain off. Otherwise, the gates are enabled and complementary or open-
drain operation is possible.
6.5.1.3
Complementary Output Mode
For complementary output mode, the gates that control Q1 and Q2 must be enabled. The Q2 gate
is always enabled (except when RESET#, HOLD#, IDLE, or POWERDOWN is asserted). Either
clearing EP_DIR (selecting complementary mode) or setting EP_MODE (selecting address
mode) enables the logic gate preceding Q1. The value of DATA determines which transistor is
turned on. If DATA is equal to one, Q1 is turned on and the pin is pulled high. If DATA is equal
to zero, Q2 is turned on and the pin is pulled low.
6.5.1.4
Open-drain Output Mode
For open-drain output mode, the gate that controls Q1 must be disabled. Setting EP_DIR (select-
ing open-drain mode) and clearing EP_MODE (selecting I/O mode) disables the logic gate pre-
ceding Q1. The value of DATA determines whether Q2 is turned on. If DATA is equal to one, both
Q1 and Q2 remain off and the pin is left in high-impedance state (floating). If DATA is equal to
zero, Q2 is turned on and the pin is pulled low.
Summary of Contents for 8XC196NT
Page 1: ...8XC196NT Microcontroller User s Manual...
Page 2: ...8XC196NT Microcontroller User s Manual June 1995 Order Number 272317 003...
Page 22: ...1 Guide to This Manual...
Page 23: ......
Page 35: ......
Page 36: ...2 Architectural Overview...
Page 37: ......
Page 49: ......
Page 50: ...3 Programming Considerations...
Page 51: ......
Page 66: ...4 Memory Partitions...
Page 67: ......
Page 104: ...5 Standard and PTS Interrupts...
Page 105: ......
Page 147: ......
Page 148: ...6 I O Ports...
Page 149: ......
Page 176: ...7 Serial I O SIO Port...
Page 177: ......
Page 194: ...8 Synchronous Serial I O SSIO Port...
Page 195: ......
Page 211: ......
Page 212: ...9 Slave Port...
Page 213: ......
Page 231: ......
Page 232: ...10 Event Processor Array EPA...
Page 233: ......
Page 270: ...11 Analog to digital Converter...
Page 271: ......
Page 291: ......
Page 292: ...12 Minimum Hardware Considerations...
Page 293: ......
Page 306: ...13 Special Operating Modes...
Page 307: ......
Page 317: ......
Page 318: ...14 Interfacing with External Memory...
Page 319: ......
Page 362: ...15 Programming the Nonvolatile Memory...
Page 363: ......
Page 408: ...A Instruction Set Reference...
Page 409: ......
Page 476: ...B Signal Descriptions...
Page 477: ......
Page 493: ......
Page 494: ...C Registers...
Page 495: ......
Page 565: ......
Page 566: ...Glossary...
Page 567: ......
Page 580: ...Index...
Page 581: ......
Page 597: ......