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8XC196NT USER’S MANUAL
Index-6
slave programming circuit, 15-16
UPROM considerations, 15-7
HLDA#, 14-4, 14-19, B-7
considerations, 6-12
HLDEN bit, 4-16, 14-21
Hold latency, See bus-hold protocol
HOLD#, 14-4, 14-19, B-7
considerations, 6-11
Hypertext manuals and datasheets, downloading,
1-10
I
I/O ports‚ See ports‚ SIO port‚ SSIO port
IBE flag, C-51
IBSP196, 15-31
Idle mode, 2-10, 12-12, 13-3–13-4
entering, 13-4
exiting, 13-4
pin status, B-14
timeout control, 10-7
IDLPD instruction, A-2, A-20, A-51, A-58, A-66
IDLPD #1, 13-4
IDLPD #2, 13-5
illegal operand, 12-9, 12-12
Immediate addressing, 3-7
INC instruction, A-2, A-20, A-46, A-52, A-59
INCB instruction, A-2, A-21, A-46, A-52, A-59
Indexed addressing, 3-11
and register RAM, 4-13
and windows, 4-22
Indirect addressing, 3-7
and register RAM, 4-13
with autoincrement, 3-8
Input pins
level-sensitive, B-4
sampled, B-4
unused, 12-2
INST, 14-4
idle, powerdown, reset status, B-14
Instruction fetch
reset location, 4-2
See also 1-Mbyte mode, 64-Kbyte mode
Instruction set, 3-1
additions, 3-5–3-6
and PSW flags, A-5
code execution, 2-4, 2-5
conventions, 1-3
differences, 3-5
execution times, A-59–A-60
lengths, A-52–A-59
opcode map, A-2–A-3
opcodes, A-46–A-51
overview, 3-1–3-5
protected instructions, 5-8
reference, A-1–A-3
See also RISM
INTEGER, defined, 3-3
Interrupts, 5-1–5-41
and bus-hold, See bus-hold protocol
controller, 2-5, 5-1
end-of-PTS, 5-19
inhibiting, 5-8
latency, 5-7–5-10, 5-24
calculating, 5-8
multiplexed, 10-29
priorities, 10-30
pending registers‚ See EPA_PEND,
EPA_PEND1, INT_PEND,
INT_PEND1
priorities, 5-4, 5-5
modifying, 5-14–5-16
procedures, PLM-96, 3-13
processing, 5-2
programming, 5-10–5-16
selecting PTS or standard service, 5-10
service routine
processing, 5-15
sources, 5-5
unused inputs, 12-2
vectors, 4-7, 5-1, 5-5
memory locations, 4-6, 4-7
INT_MASK, 10-4, 13-2
INT_MASK1, 5-3
INT_PEND, 10-4, 13-2
INT_PEND1, 5-4
Italics, defined, 1-4
J
JBC instruction, A-2, A-5, A-21, A-46, A-57, A-65
JBS instruction, A-3, A-5, A-21, A-46, A-57, A-65
JC instruction, A-3, A-5, A-22, A-50, A-57, A-65
JE instruction, A-3, A-5, A-22, A-50, A-57, A-65
JGE instruction, A-2, A-5, A-22, A-50, A-57, A-65
JGT instruction, A-2, A-5, A-23, A-50, A-57, A-65
Summary of Contents for 8XC196NT
Page 1: ...8XC196NT Microcontroller User s Manual...
Page 2: ...8XC196NT Microcontroller User s Manual June 1995 Order Number 272317 003...
Page 22: ...1 Guide to This Manual...
Page 23: ......
Page 35: ......
Page 36: ...2 Architectural Overview...
Page 37: ......
Page 49: ......
Page 50: ...3 Programming Considerations...
Page 51: ......
Page 66: ...4 Memory Partitions...
Page 67: ......
Page 104: ...5 Standard and PTS Interrupts...
Page 105: ......
Page 147: ......
Page 148: ...6 I O Ports...
Page 149: ......
Page 176: ...7 Serial I O SIO Port...
Page 177: ......
Page 194: ...8 Synchronous Serial I O SSIO Port...
Page 195: ......
Page 211: ......
Page 212: ...9 Slave Port...
Page 213: ......
Page 231: ......
Page 232: ...10 Event Processor Array EPA...
Page 233: ......
Page 270: ...11 Analog to digital Converter...
Page 271: ......
Page 291: ......
Page 292: ...12 Minimum Hardware Considerations...
Page 293: ......
Page 306: ...13 Special Operating Modes...
Page 307: ......
Page 317: ......
Page 318: ...14 Interfacing with External Memory...
Page 319: ......
Page 362: ...15 Programming the Nonvolatile Memory...
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Page 408: ...A Instruction Set Reference...
Page 409: ......
Page 476: ...B Signal Descriptions...
Page 477: ......
Page 493: ......
Page 494: ...C Registers...
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Page 565: ......
Page 566: ...Glossary...
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Page 580: ...Index...
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